Chung-Wen Tsao

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Two-stage clock tree synthesis with buffer distribution balancing
- Patent number 7,051,310
- Issue date May 23, 2006
- Cadence Design Systems, Inc.
- Chung-wen Tsao
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Two-stage clock tree synthesis
- Publication number 20040225984
- Publication date Nov 11, 2004
- Chung-Wen Tsao
- G06 - COMPUTING CALCULATING COUNTING