Chung Y. Yip

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Aloha, OR, US

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Patents Grantslast 30 patents

Information Patent Grant
Method for shrinking a clock cycle when testing high speed micropro...
- Patent number 5,661,731
- Issue date Aug 26, 1997
- Intel Corporation
- Chung Yin Joseph Yip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast parity generator using complement pass-transistor logic
- Patent number 5,608,741
- Issue date Mar 4, 1997
- Intel Corporation
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING