Cindy ShuiKing Washburn

Person

Poughquag, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Routing layer re-optimization in physical synthesis
- Patent number 11,983,477
- Issue date May 14, 2024
- International Business Machines Corporation
- Lakshmi N. Reddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Boundary assertion-based power recovery in integrated circuit design
- Patent number 10,706,194
- Issue date Jul 7, 2020
- International Business Machines Corporation
- Alexander J. Suess
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic microprocessor gate design tool for area/timing margin control
- Patent number 10,671,791
- Issue date Jun 2, 2020
- International Business Machines Corporation
- Michael A. Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Critical path straightening system based on free-space aware and ti...
- Patent number 10,216,882
- Issue date Feb 26, 2019
- International Business Machines Corporation
- Jinwook Jung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic microprocessor gate design tool for area/timing margin control
- Patent number 10,078,722
- Issue date Sep 18, 2018
- International Business Machines Corporation
- Michael A. Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid linear wire model approach to tuning transistor widths of ci...
- Patent number 7,325,210
- Issue date Jan 29, 2008
- International Business Machines Corporation
- Vasant Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for tuning a digital design for synthesized random logic cir...
- Patent number 7,093,208
- Issue date Aug 15, 2006
- International Business Machines Corporation
- Patrick M. Williams
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ROUTING LAYER RE-OPTIMIZATION IN PHYSICAL SYNTHESIS
- Publication number 20230059055
- Publication date Feb 23, 2023
- International Business Machines Corporation
- Lakshmi N. Reddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOUNDARY ASSERTION-BASED POWER RECOVERY IN INTEGRATED CIRCUIT DESIGN
- Publication number 20200089828
- Publication date Mar 19, 2020
- International Business Machines Corporation
- Alexander J. Suess
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC MICROPROCESSOR GATE DESIGN TOOL FOR AREA/TIMING MARGIN CONTROL
- Publication number 20180330039
- Publication date Nov 15, 2018
- International Business Machines Corporation
- Michael A. Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRITICAL PATH STRAIGHTENING SYSTEM BASED ON FREE-SPACE AWARE AND TI...
- Publication number 20180121575
- Publication date May 3, 2018
- International Business Machines Corporation
- Jinwook Jung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC MICROPROCESSOR GATE DESIGN TOOL FOR AREA/TIMING MARGIN CONTROL
- Publication number 20170357747
- Publication date Dec 14, 2017
- International Business Machines Corporation
- Michael A. Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hybrid linear wire model approach to tuning transistor widths of ci...
- Publication number 20060206845
- Publication date Sep 14, 2006
- International Business Machines Corporation
- Vasant Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for tuning a digital design for synthesized random logic cir...
- Publication number 20040230924
- Publication date Nov 18, 2004
- International Business Machines Corporation
- Patrick M. Williams
- G06 - COMPUTING CALCULATING COUNTING

Cindy ShuiKing Washburn

Person

Patents Grantslast 30 patents

Routing layer re-optimization in physical synthesis

Boundary assertion-based power recovery in integrated circuit design

Dynamic microprocessor gate design tool for area/timing margin control

Critical path straightening system based on free-space aware and ti...

Dynamic microprocessor gate design tool for area/timing margin control

Hybrid linear wire model approach to tuning transistor widths of ci...

Method for tuning a digital design for synthesized random logic cir...

Patents Applicationslast 30 patents

ROUTING LAYER RE-OPTIMIZATION IN PHYSICAL SYNTHESIS

BOUNDARY ASSERTION-BASED POWER RECOVERY IN INTEGRATED CIRCUIT DESIGN

DYNAMIC MICROPROCESSOR GATE DESIGN TOOL FOR AREA/TIMING MARGIN CONTROL

CRITICAL PATH STRAIGHTENING SYSTEM BASED ON FREE-SPACE AWARE AND TI...

DYNAMIC MICROPROCESSOR GATE DESIGN TOOL FOR AREA/TIMING MARGIN CONTROL

Hybrid linear wire model approach to tuning transistor widths of ci...

Method for tuning a digital design for synthesized random logic cir...