Claudio Brambilla

Person

Concorezzo, IT

People

Patents Grantslast 30 patents

Information Patent Grant
Process for manufacturing a dual charge storage location memory cell
- Patent number 7,115,472
- Issue date Oct 3, 2006
- STMicroelectronics, SRL
- Paolo Caprara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for manufacturing a dual charge storage location memory cell
- Patent number 6,825,523
- Issue date Nov 30, 2004
- STMicroelectronics S.r.l.
- Paolo Caprara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for manufacturing semiconductor integrated memory devices w...
- Patent number 6,365,456
- Issue date Apr 2, 2002
- STMicroelectronics, SRL
- Manlio Sergio Cereda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for manufacturing an integrated circuit comprising an array...
- Patent number 6,353,243
- Issue date Mar 5, 2002
- SGS-Thomson Microelectronics S.r.l.
- Claudio Brambilla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for autoaligning overlapped lines of a conductive material i...
- Patent number 6,350,671
- Issue date Feb 26, 2002
- STMicroelectronics S.r.l.
- Claudio Brambilla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing an EPROM memory device having memory cells...
- Patent number 6,326,266
- Issue date Dec 4, 2001
- STMicroelectronics S.r.l.
- Claudio Brambilla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for manufacturing semiconductor integrated memory devices w...
- Patent number 6,300,195
- Issue date Oct 9, 2001
- STMicroelectronics, SRL
- Pierantonio Pozzoni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming contactless MOS transistors and resulting device...
- Patent number 6,251,736
- Issue date Jun 26, 2001
- STMicroelectronics S.r.l.
- Claudio Brambilla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for improving the intermediate dielectric profile, particula...
- Patent number 6,104,058
- Issue date Aug 15, 2000
- SGS Thomson Microelectronics S.r.l.
- Claudio Brambilla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a native MOS P-channel transistor with a p...
- Patent number 6,063,663
- Issue date May 16, 2000
- SGS-Thomson Microelectronics S.r.L.
- Paolo Caprara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for manufacturing an integrated circuit comprising an array...
- Patent number 5,976,933
- Issue date Nov 2, 1999
- SGS Thomson Microelectronics S.r.l.
- Claudio Brambilla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for improving the intermediate dielectric profile, particula...
- Patent number 5,894,065
- Issue date Apr 13, 1999
- SGS Thomson Microelectronics S.r.l.
- Claudio Brambilla
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Process for manufacturing a dual charge storage location memory cell
- Publication number 20050064654
- Publication date Mar 24, 2005
- STMicroelectronics S.r.l.
- Paolo Caprara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for manufacturing a dual charge storage location memory cell
- Publication number 20030067032
- Publication date Apr 10, 2003
- STMicroelectronics S.r.I.
- Paolo Caprara
- H01 - BASIC ELECTRIC ELEMENTS

Claudio Brambilla

Person

Patents Grantslast 30 patents

Process for manufacturing a dual charge storage location memory cell

Process for manufacturing a dual charge storage location memory cell

Process for manufacturing semiconductor integrated memory devices w...

Process for manufacturing an integrated circuit comprising an array...

Method for autoaligning overlapped lines of a conductive material i...

Method of manufacturing an EPROM memory device having memory cells...

Process for manufacturing semiconductor integrated memory devices w...

Method for forming contactless MOS transistors and resulting device...

Method for improving the intermediate dielectric profile, particula...

Method for manufacturing a native MOS P-channel transistor with a p...

Process for manufacturing an integrated circuit comprising an array...

Method for improving the intermediate dielectric profile, particula...

Patents Applicationslast 30 patents

Process for manufacturing a dual charge storage location memory cell

Process for manufacturing a dual charge storage location memory cell