Claudio Nava

Person

Cornate d'Adda (MI), IT

People

Patents Grantslast 30 patents

Information Patent Grant
Circuit partitioning for a memory device
- Patent number 12,182,432
- Issue date Dec 31, 2024
- Micron Technology, Inc.
- Andrea Martinelli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoding architecture for memory tiles
- Patent number 11,804,264
- Issue date Oct 31, 2023
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoding architecture for memory tiles
- Patent number 11,475,947
- Issue date Oct 18, 2022
- Micron Technology, Inc.
- Paolo Fantini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit partitioning for a memory device
- Patent number 11,144,228
- Issue date Oct 12, 2021
- Micron Technology, Inc.
- Andrea Martinelli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Row selector occupying a reduced device area for semiconductor memo...
- Patent number 7,965,561
- Issue date Jun 21, 2011
- Micron Technology, Inc.
- Pierguido Garofalo
- G11 - INFORMATION STORAGE
Information Patent Grant
Transmission line system for a digital signal having a transfer bus...
- Patent number 7,911,290
- Issue date Mar 22, 2011
- STMicroelectronics S.r.l.
- Daniele Vimercati
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory device employing three-level cells and related methods of ma...
- Patent number 7,596,023
- Issue date Sep 29, 2009
- Alessandro Magnavacca
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device with selectable pads
- Patent number 6,339,551
- Issue date Jan 15, 2002
- STMicroelectronics S.r.l.
- Simone Bartoli
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DECODING ARCHITECTURE FOR MEMORY TILES
- Publication number 20230071663
- Publication date Mar 9, 2023
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Application
DECODING ARCHITECTURE FOR MEMORY TILES
- Publication number 20220336015
- Publication date Oct 20, 2022
- Micron Technology, Inc.
- Paolo Fantini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUIT PARTITIONING FOR A MEMORY DEVICE
- Publication number 20220100404
- Publication date Mar 31, 2022
- Micron Technology, Inc.
- Andrea Martinelli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT PARTITIONING FOR A MEMORY DEVICE
- Publication number 20210011645
- Publication date Jan 14, 2021
- Micron Technology, Inc.
- Andrea Martinelli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE EMPLOYING THREE-LEVEL CELLS AND RELATED METHODS OF MA...
- Publication number 20080106937
- Publication date May 8, 2008
- STMicroelectronics S.r.I.
- Alessandro MAGNAVACCA
- G11 - INFORMATION STORAGE
Information Patent Application
ROW SELECTOR WITH REDUCED AREA OCCUPATION FOR SEMICONDUCTOR MEMORY...
- Publication number 20070195605
- Publication date Aug 23, 2007
- STMicroelectronics S.r.l.
- Pierguido Garofalo
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSMISSION SYSTEM OF A DIGITAL SIGNAL
- Publication number 20070133666
- Publication date Jun 14, 2007
- STMicroelectronics S.r.l.
- Daniele Vimercati
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Claudio Nava

Person

Patents Grantslast 30 patents

Circuit partitioning for a memory device

Decoding architecture for memory tiles

Decoding architecture for memory tiles

Circuit partitioning for a memory device

Row selector occupying a reduced device area for semiconductor memo...

Transmission line system for a digital signal having a transfer bus...

Memory device employing three-level cells and related methods of ma...

Semiconductor device with selectable pads

Patents Applicationslast 30 patents

DECODING ARCHITECTURE FOR MEMORY TILES

DECODING ARCHITECTURE FOR MEMORY TILES

CIRCUIT PARTITIONING FOR A MEMORY DEVICE

CIRCUIT PARTITIONING FOR A MEMORY DEVICE

MEMORY DEVICE EMPLOYING THREE-LEVEL CELLS AND RELATED METHODS OF MA...

ROW SELECTOR WITH REDUCED AREA OCCUPATION FOR SEMICONDUCTOR MEMORY...

TRANSMISSION SYSTEM OF A DIGITAL SIGNAL