Clinton Chao

Person

Redwood Shores, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods of manufacturing an integrated circuit having stress tuning...
- Patent number 11,935,842
- Issue date Mar 19, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of manufacturing an integrated circuit having stress tuning...
- Patent number 11,094,646
- Issue date Aug 17, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of manufacturing an integrated circuit having stress tuning...
- Patent number 10,269,730
- Issue date Apr 23, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of manufacturing an integrated circuit having stress tuning...
- Patent number 9,633,954
- Issue date Apr 25, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit having stress tuning layer
- Patent number 9,275,948
- Issue date Mar 1, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable semiconductor interposer for electronic package and me...
- Patent number 8,945,998
- Issue date Feb 3, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chao-Shun Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon-based thin substrate and packaging schemes
- Patent number 8,704,383
- Issue date Apr 22, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Szu-Wei Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming stacked-die packages
- Patent number 8,426,256
- Issue date Apr 23, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- C. W. Hsiao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing integrated circuit having stress tuning layer
- Patent number 8,367,474
- Issue date Feb 5, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Methods of Manufacturing An Integrated Circuit Having Stress Tuning...
- Publication number 20210375789
- Publication date Dec 2, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of Manufacturing an Integrated Circuit Having Stress Tuning...
- Publication number 20190252328
- Publication date Aug 15, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of Manufacturing An Integrated Circuit Having Stress Tuning...
- Publication number 20170229403
- Publication date Aug 10, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Having Stress Tuning Layer and Methods of Manufa...
- Publication number 20160181209
- Publication date Jun 23, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Programmable Semiconductor Interposer for Electronic Package and Me...
- Publication number 20130295727
- Publication date Nov 7, 2013
- Chao-Shun Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Having Stress Tuning Layer and Methods of Manufa...
- Publication number 20130140715
- Publication date Jun 6, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicon-Based Thin Substrate and Packaging Schemes
- Publication number 20120199974
- Publication date Aug 9, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Szu Wei Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Having Stress Tuning Layer and Methods of Manufa...
- Publication number 20110097893
- Publication date Apr 28, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING STACKED-DIE PACKAGES
- Publication number 20100279463
- Publication date Nov 4, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- C. W. Hsiao
- H01 - BASIC ELECTRIC ELEMENTS

Clinton Chao

Person

Patents Grantslast 30 patents

Methods of manufacturing an integrated circuit having stress tuning...

Methods of manufacturing an integrated circuit having stress tuning...

Methods of manufacturing an integrated circuit having stress tuning...

Methods of manufacturing an integrated circuit having stress tuning...

Integrated circuit having stress tuning layer

Programmable semiconductor interposer for electronic package and me...

Silicon-based thin substrate and packaging schemes

Method of forming stacked-die packages

Method of manufacturing integrated circuit having stress tuning layer

Patents Applicationslast 30 patents

Methods of Manufacturing An Integrated Circuit Having Stress Tuning...

Methods of Manufacturing an Integrated Circuit Having Stress Tuning...

Methods of Manufacturing An Integrated Circuit Having Stress Tuning...

Integrated Circuit Having Stress Tuning Layer and Methods of Manufa...

Programmable Semiconductor Interposer for Electronic Package and Me...

Integrated Circuit Having Stress Tuning Layer and Methods of Manufa...

Silicon-Based Thin Substrate and Packaging Schemes

Integrated Circuit Having Stress Tuning Layer and Methods of Manufa...

METHOD OF FORMING STACKED-DIE PACKAGES