Colin Yates

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of aligning nanotubes and wires with an etched feature
- Patent number 8,343,373
- Issue date Jan 1, 2013
- Nantero Inc.
- Colin D. Yates
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method of aligning deposited nanotubes onto an etched feature using...
- Patent number 7,858,979
- Issue date Dec 28, 2010
- Nantero, Inc.
- Colin D. Yates
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of aligning nanotubes and wires with an etched feature
- Patent number 7,575,693
- Issue date Aug 18, 2009
- Nantero, Inc.
- Colin D. Yates
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of aligning deposited nanotubes onto an etched feature using...
- Patent number 7,541,216
- Issue date Jun 2, 2009
- Nantero, Inc.
- Colin D. Yates
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Alignment process for integrated circuit structures on semiconducto...
- Patent number 6,809,824
- Issue date Oct 26, 2004
- LSI Logic Corporation
- Colin D. Yates
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of protecting acid-catalyzed photoresist from chip-generated...
- Patent number 6,458,508
- Issue date Oct 1, 2002
- LSI Logic Corporation
- Nicholas F. Pasch
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
System and method for performing optical proximity correction on th...
- Patent number 6,425,117
- Issue date Jul 23, 2002
- LSI Logic Corporation
- Nicholas F. Pasch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Alignment mark contrast enhancement
- Patent number 5,863,825
- Issue date Jan 26, 1999
- LSI Logic Corporation
- Nicholas F. Pasch
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF ALIGNING NANOTUBES AND WIRES WITH AN ETCHED FEATURE
- Publication number 20090314530
- Publication date Dec 24, 2009
- Nantero, Inc.
- Colin D. YATES
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHOD OF ALIGNING DEPOSITED NANOTUBES ONTO AN ETCHED FEATURE USING...
- Publication number 20090243102
- Publication date Oct 1, 2009
- Nantero, Inc.
- Colin D. Yates
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of aligning deposited nanotubes onto an etched feature using...
- Publication number 20060281287
- Publication date Dec 14, 2006
- Colin D. Yates
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of aligning nanotubes and wires with an etched feature
- Publication number 20060264053
- Publication date Nov 23, 2006
- LSI Logic Corporation
- Colin D. Yates
- B82 - NANO-TECHNOLOGY

Colin Yates

Person

Patents Grantslast 30 patents

Method of aligning nanotubes and wires with an etched feature

Method of aligning deposited nanotubes onto an etched feature using...

Method of aligning nanotubes and wires with an etched feature

Method of aligning deposited nanotubes onto an etched feature using...

Alignment process for integrated circuit structures on semiconducto...

Method of protecting acid-catalyzed photoresist from chip-generated...

System and method for performing optical proximity correction on th...

Alignment mark contrast enhancement

Patents Applicationslast 30 patents

METHOD OF ALIGNING NANOTUBES AND WIRES WITH AN ETCHED FEATURE

METHOD OF ALIGNING DEPOSITED NANOTUBES ONTO AN ETCHED FEATURE USING...

Method of aligning deposited nanotubes onto an etched feature using...

Method of aligning nanotubes and wires with an etched feature