Colyn Case

Person

Grass Valley, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
PCIE clock rate stepping for graphics and platform processors
- Patent number 9,262,837
- Issue date Feb 16, 2016
- NVIDIA Corporation
- Anthony Michael Tamasi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Consolidated crossbar that supports a multitude of traffic types
- Patent number 9,098,383
- Issue date Aug 4, 2015
- NVIDIA Corporation
- Sean J. Treichler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Efficient memory translator with variable size cache line coverage
- Patent number 8,341,380
- Issue date Dec 25, 2012
- NVIDIA Corporation
- James Leroy Deming
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory interface with dynamic selection among mirrored storage loca...
- Patent number 8,161,252
- Issue date Apr 17, 2012
- NVIDIA Corporation
- Colyn S. Case
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Raster operations unit with interleaving of read and write requests...
- Patent number 8,035,647
- Issue date Oct 11, 2011
- NVIDIA Corporation
- Donald A. Bittel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory management for virtual address space with translation units...
- Patent number 7,797,510
- Issue date Sep 14, 2010
- NVIDIA Corporation
- Colyn S. Case
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asymmetrical bus for bus link width optimization of a graphics system
- Patent number 7,788,439
- Issue date Aug 31, 2010
- NVIDIA Corporation
- William P. Tsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Page stream sorter for poor locality access patterns
- Patent number 7,664,905
- Issue date Feb 16, 2010
- NVIDIA Corporation
- David A. Jarosh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control device for data stream optimizations in a link interface
- Patent number 7,624,221
- Issue date Nov 24, 2009
- NVIDIA Corporation
- Colyn S. Case
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual address translation system with caching of variable-range t...
- Patent number 7,562,205
- Issue date Jul 14, 2009
- NVIDIA Corporation
- Colyn S. Case
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packet combiner for a packetized bus with dynamic holdoff time
- Patent number 7,526,593
- Issue date Apr 28, 2009
- NVIDIA Corporation
- Manas Mandal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asymmetrical bus
- Patent number 7,469,311
- Issue date Dec 23, 2008
- NVIDIA Corporation
- William P. Tsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared cache with client-specific replacement policy
- Patent number 7,415,575
- Issue date Aug 19, 2008
- NVIDIA, Corporation
- Peter C. Tong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory management for virtual address space with translation units...
- Patent number 7,386,697
- Issue date Jun 10, 2008
- NVIDIA Corporation
- Colyn S. Case
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-client virtual address translation system with translation un...
- Patent number 7,334,108
- Issue date Feb 19, 2008
- NVIDIA Corporation
- Colyn S. Case
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-memory table structure for virtual address translation system wi...
- Patent number 7,296,139
- Issue date Nov 13, 2007
- NVIDIA Corporation
- Colyn S. Case
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual address translation system with caching of variable-range t...
- Patent number 7,278,008
- Issue date Oct 2, 2007
- NVIDIA Corporation
- Colyn S. Case
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data prefetcher with predictor capabilities
- Patent number 6,820,173
- Issue date Nov 16, 2004
- NVIDIA Corporation
- Donald A. Bittel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-throughput interconnect having pipelined and non-pipelined bus...
- Patent number 6,317,803
- Issue date Nov 13, 2001
- Intel Corporation
- Norman J. Rasmussen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for placement of operands in system memory
- Patent number 6,097,402
- Issue date Aug 1, 2000
- Intel Corporation
- Colyn Case
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory handling system that backfills dual-port buffer from overflo...
- Patent number 6,044,419
- Issue date Mar 28, 2000
- Intel Corporation
- George Hayek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-throughput interconnect allowing bus transactions based on par...
- Patent number 5,911,051
- Issue date Jun 8, 1999
- Intel Corporation
- David G. Carson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for transmitting graphics command in a compute...
- Patent number 5,321,806
- Issue date Jun 14, 1994
- Digital Equipment Corporation
- Kim Meinerth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address method for computer graphics system
- Patent number 5,321,810
- Issue date Jun 14, 1994
- Digital Equipment Corporation
- Colyn Case
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Method and apparatus for varying command length in a computer graph...
- Patent number 5,315,698
- Issue date May 24, 1994
- Digital Equipment Corporation
- Colyn Case
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Graphics command processing method in a computer graphics system
- Patent number 5,315,696
- Issue date May 24, 1994
- Digital Equipment Corporation
- Colyn Case
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Translation of virtual addresses in a computer graphics system
- Patent number 5,313,577
- Issue date May 17, 1994
- Digital Equipment Corporation
- Kim Meinerth
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PCIE CLOCK RATE STEPPING FOR GRAPHICS AND PLATFORM PROCESSORS
- Publication number 20150199822
- Publication date Jul 16, 2015
- NVIDIA Corporation
- Anthony Michael Tamasi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT MEMORY TRANSLATOR WITH VARIABLE SIZE CACHE LINE COVERAGE
- Publication number 20110072235
- Publication date Mar 24, 2011
- James Leroy Deming
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Page stream sorter for poor locality access patterns
- Publication number 20080109613
- Publication date May 8, 2008
- NVIDIA Corporation
- David A. Jarosh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEDICATED MECHANISM FOR PAGE MAPPING IN A GPU
- Publication number 20080028181
- Publication date Jan 31, 2008
- NVIDIA Corporation
- Peter C. Tong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Packet Combiner for a Packetized Bus with Dynamic Holdoff time
- Publication number 20070079044
- Publication date Apr 5, 2007
- NVIDIA Corporation
- Manas Mandal
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

PCIE clock rate stepping for graphics and platform processors

Consolidated crossbar that supports a multitude of traffic types

Efficient memory translator with variable size cache line coverage

Memory interface with dynamic selection among mirrored storage loca...

Raster operations unit with interleaving of read and write requests...

Memory management for virtual address space with translation units...

Asymmetrical bus for bus link width optimization of a graphics system

Page stream sorter for poor locality access patterns

Control device for data stream optimizations in a link interface

Virtual address translation system with caching of variable-range t...

Packet combiner for a packetized bus with dynamic holdoff time

Asymmetrical bus

Shared cache with client-specific replacement policy

Memory management for virtual address space with translation units...

Multi-client virtual address translation system with translation un...

In-memory table structure for virtual address translation system wi...

Virtual address translation system with caching of variable-range t...

Data prefetcher with predictor capabilities

High-throughput interconnect having pipelined and non-pipelined bus...

System and method for placement of operands in system memory

Memory handling system that backfills dual-port buffer from overflo...

High-throughput interconnect allowing bus transactions based on par...

Method and apparatus for transmitting graphics command in a compute...

Address method for computer graphics system

Method and apparatus for varying command length in a computer graph...

Graphics command processing method in a computer graphics system

Translation of virtual addresses in a computer graphics system

Patents Applicationslast 30 patents

PCIE CLOCK RATE STEPPING FOR GRAPHICS AND PLATFORM PROCESSORS

EFFICIENT MEMORY TRANSLATOR WITH VARIABLE SIZE CACHE LINE COVERAGE

Page stream sorter for poor locality access patterns

DEDICATED MECHANISM FOR PAGE MAPPING IN A GPU

Packet Combiner for a Packetized Bus with Dynamic Holdoff time