Conrado Blasco

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Compressing translation lookaside buffer (TLB) tags using a TLB met...
- Patent number 12,130,751
- Issue date Oct 29, 2024
- QUALCOMM Incorporated
- Adrian Montero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latency management in synchronization events
- Patent number 11,914,524
- Issue date Feb 27, 2024
- QUALCOMM Incorporated
- Adrian Montero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for optimizing authentication branch instructions
- Patent number 11,468,168
- Issue date Oct 11, 2022
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Indirect branch predictor storing encrypted branch information fiel...
- Patent number 11,449,343
- Issue date Sep 20, 2022
- Apple Inc.
- Jeffry E. Gonion
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zero cycle load bypass in a decode group
- Patent number 11,416,254
- Issue date Aug 16, 2022
- Apple Inc.
- Deepankar Duggal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Indirect branch predictor based on register operands
- Patent number 11,379,240
- Issue date Jul 5, 2022
- Apple Inc.
- Muawya M. Al-Otoom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
History file for previous register mapping storage and last referen...
- Patent number 11,200,062
- Issue date Dec 14, 2021
- Apple Inc.
- Deepankar Duggal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for partially preserving a branch predictor state
- Patent number 11,093,249
- Issue date Aug 17, 2021
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fetch predition circuit for reducing power consumption in a processor
- Patent number 10,901,484
- Issue date Jan 26, 2021
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Marking valid return targets
- Patent number 10,867,031
- Issue date Dec 15, 2020
- Apple Inc.
- Gregory D. Hughes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speculative writes to special-purpose register
- Patent number 10,838,723
- Issue date Nov 17, 2020
- Apple Inc.
- Christopher M. Tsay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for predicting memory dependence when a source re...
- Patent number 10,838,729
- Issue date Nov 17, 2020
- Apple Inc.
- Muawya M. Al-Otoom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Branch prediction system
- Patent number 10,719,327
- Issue date Jul 21, 2020
- Apple Inc.
- Muawya M. Al-Otoom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical reservation station
- Patent number 10,452,434
- Issue date Oct 22, 2019
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing power consumption in a processor
- Patent number 10,241,557
- Issue date Mar 26, 2019
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for partially saving a branch predictor state
- Patent number 10,223,123
- Issue date Mar 5, 2019
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storing taken branch information
- Patent number 10,175,982
- Issue date Jan 8, 2019
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Program counter capturing
- Patent number 9,952,863
- Issue date Apr 24, 2018
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Immediate branch recode that handles aliasing
- Patent number 9,940,262
- Issue date Apr 10, 2018
- Apple Inc.
- Shyam Sundar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Split register file for operands of different sizes
- Patent number 9,639,369
- Issue date May 2, 2017
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for allowing speculative execution of loads beyond a wait...
- Patent number 9,501,284
- Issue date Nov 22, 2016
- Apple Inc.
- Pradeep Kanapathipillai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Early loop buffer mode entry upon number of mispredictions of exit...
- Patent number 9,471,322
- Issue date Oct 18, 2016
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
EXPLOITING VIRTUAL ADDRESS (VA) SPATIAL LOCALITY USING TRANSLATION...
- Publication number 20240273035
- Publication date Aug 15, 2024
- QUALCOMM Incorporated
- Adrian Montero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSING TRANSLATION LOOKASIDE BUFFER (TLB) TAGS USING A TLB MET...
- Publication number 20240273034
- Publication date Aug 15, 2024
- QUALCOMM Incorporated
- Adrian Montero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSING TRANSLATION LOOKASIDE BUFFER (TLB) TAGS USING A TLB MET...
- Publication number 20240273036
- Publication date Aug 15, 2024
- QUALCOMM Incorporated
- Adrian Montero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXPLOITING VIRTUAL ADDRESS (VA) SPATIAL LOCALITY USING TRANSLATION...
- Publication number 20240273033
- Publication date Aug 15, 2024
- QUALCOMM Incorporated
- Adrian Montero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING RETIRED PAGES HISTORY FOR INSTRUCTION TRANSLATION LOOKASIDE B...
- Publication number 20240264949
- Publication date Aug 8, 2024
- QUALCOMM Incorporated
- Ajay Kumar Rathee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MITIGATING POINTER AUTHENTICATION CODE (PAC) ATTACKS IN PROCESSOR-B...
- Publication number 20240241951
- Publication date Jul 18, 2024
- QUALCOMM Incorporated
- Jamie David Iles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MITIGATING POINTER AUTHENTICATION CODE (PAC) ATTACKS IN PROCESSOR-B...
- Publication number 20240086526
- Publication date Mar 14, 2024
- QUALCOMM Incorporated
- Jamie David Iles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING RETIRED PAGES HISTORY FOR INSTRUCTION TRANSLATION LOOKASIDE B...
- Publication number 20240037042
- Publication date Feb 1, 2024
- QUALCOMM Incorporated
- Ajay Kumar Rathee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latency Management in Synchronization Events
- Publication number 20230281133
- Publication date Sep 7, 2023
- NUVIA, INC.
- Adrian MONTERO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THROTTLING SCHEMES IN MULTICORE MICROPROCESSORS
- Publication number 20230176977
- Publication date Jun 8, 2023
- QUALCOMM Incorporated
- Amit Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHODS FOR INVALIDATING TRANSLATION INFORMATION IN CACHES
- Publication number 20230064603
- Publication date Mar 2, 2023
- NUVIA, INC.
- Conrado BLASCO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INDIRECT BRANCH PREDICTOR SECURITY PROTECTION
- Publication number 20230010948
- Publication date Jan 12, 2023
- Apple Inc.
- Jeffry E. Gonion
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Throttling Schemes in Multicore Microprocessors
- Publication number 20220365879
- Publication date Nov 17, 2022
- NUVIA, INC.
- Amit Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Indirect Branch Predictor Based on Register Operands
- Publication number 20210240477
- Publication date Aug 5, 2021
- Apple Inc.
- Muawya M. Al-Otoom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZERO CYCLE LOAD BYPASS
- Publication number 20210173654
- Publication date Jun 10, 2021
- Apple Inc.
- Deepankar Duggal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAST PHYSICAL REGISTER REFERENCE SCHEME
- Publication number 20210064376
- Publication date Mar 4, 2021
- Apple Inc.
- Deepankar Duggal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INDIRECT BRANCH PREDICTOR SECURITY PROTECTION
- Publication number 20200192672
- Publication date Jun 18, 2020
- Apple Inc.
- Jeffry E. Gonion
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING POWER CONSUMPTION IN A PROCESSOR
- Publication number 20190286218
- Publication date Sep 19, 2019
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR PARTIALLY SAVING A BRANCH PREDICTOR STATE
- Publication number 20190196834
- Publication date Jun 27, 2019
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MARKING VALID RETURN TARGETS
- Publication number 20170024559
- Publication date Jan 26, 2017
- Apple Inc.
- Gregory D. Hughes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR ALLOWING SPECULATIVE EXECUTION OF LOADS BEYOND A WAIT...
- Publication number 20160092236
- Publication date Mar 31, 2016
- Apple Inc.
- Pradeep Kanapathipaillai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMMEDIATE BRANCH RECODE THAT HANDLES ALIASING
- Publication number 20160085550
- Publication date Mar 24, 2016
- Apple Inc.
- Shyam Sundar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EARLY LOOP BUFFER ENTRY
- Publication number 20150227374
- Publication date Aug 13, 2015
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING POWER CONSUMPTION IN A PROCESSOR
- Publication number 20150169041
- Publication date Jun 18, 2015
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Split Register File for Operands of Different Sizes
- Publication number 20150134935
- Publication date May 14, 2015
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING

Conrado Blasco

Person

Patents Grantslast 30 patents

Compressing translation lookaside buffer (TLB) tags using a TLB met...

Latency management in synchronization events

Systems and methods for optimizing authentication branch instructions

Indirect branch predictor storing encrypted branch information fiel...

Zero cycle load bypass in a decode group

Indirect branch predictor based on register operands

History file for previous register mapping storage and last referen...

Methods for partially preserving a branch predictor state

Fetch predition circuit for reducing power consumption in a processor

Marking valid return targets

Speculative writes to special-purpose register

System and method for predicting memory dependence when a source re...

Branch prediction system

Hierarchical reservation station

Reducing power consumption in a processor

Methods for partially saving a branch predictor state

Storing taken branch information

Program counter capturing

Immediate branch recode that handles aliasing

Split register file for operands of different sizes

Mechanism for allowing speculative execution of loads beyond a wait...

Early loop buffer mode entry upon number of mispredictions of exit...

Patents Applicationslast 30 patents

EXPLOITING VIRTUAL ADDRESS (VA) SPATIAL LOCALITY USING TRANSLATION...

COMPRESSING TRANSLATION LOOKASIDE BUFFER (TLB) TAGS USING A TLB MET...

COMPRESSING TRANSLATION LOOKASIDE BUFFER (TLB) TAGS USING A TLB MET...

EXPLOITING VIRTUAL ADDRESS (VA) SPATIAL LOCALITY USING TRANSLATION...

USING RETIRED PAGES HISTORY FOR INSTRUCTION TRANSLATION LOOKASIDE B...

MITIGATING POINTER AUTHENTICATION CODE (PAC) ATTACKS IN PROCESSOR-B...

MITIGATING POINTER AUTHENTICATION CODE (PAC) ATTACKS IN PROCESSOR-B...

USING RETIRED PAGES HISTORY FOR INSTRUCTION TRANSLATION LOOKASIDE B...

Latency Management in Synchronization Events

THROTTLING SCHEMES IN MULTICORE MICROPROCESSORS

SYSTEM AND METHODS FOR INVALIDATING TRANSLATION INFORMATION IN CACHES

INDIRECT BRANCH PREDICTOR SECURITY PROTECTION

Throttling Schemes in Multicore Microprocessors

Indirect Branch Predictor Based on Register Operands

ZERO CYCLE LOAD BYPASS

LAST PHYSICAL REGISTER REFERENCE SCHEME

INDIRECT BRANCH PREDICTOR SECURITY PROTECTION

REDUCING POWER CONSUMPTION IN A PROCESSOR

METHODS FOR PARTIALLY SAVING A BRANCH PREDICTOR STATE

MARKING VALID RETURN TARGETS

MECHANISM FOR ALLOWING SPECULATIVE EXECUTION OF LOADS BEYOND A WAIT...

IMMEDIATE BRANCH RECODE THAT HANDLES ALIASING

EARLY LOOP BUFFER ENTRY

REDUCING POWER CONSUMPTION IN A PROCESSOR

Split Register File for Operands of Different Sizes