Craig Barner

Person

Shrewsbury, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low latency inter-chip communication mechanism in a multi-chip proc...
- Patent number 12,019,552
- Issue date Jun 25, 2024
- Marvell Asia Pte, Ltd.
- Craig Barner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low latency inter-chip communication mechanism in a multi-chip proc...
- Patent number 11,620,223
- Issue date Apr 4, 2023
- Marvell Asia Pte, Ltd.
- Craig Barner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low latency inter-chip communication mechanism in multi-chip proces...
- Patent number 11,119,929
- Issue date Sep 14, 2021
- Marvell Asia Pte, Ltd.
- Craig Barner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit error rate impact reduction
- Patent number 9,065,626
- Issue date Jun 23, 2015
- Cavium, Inc.
- Craig Barner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Word boundary lock
- Patent number 9,059,836
- Issue date Jun 16, 2015
- Cavium, Inc.
- Craig Barner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Word boundary lock
- Patent number 8,855,248
- Issue date Oct 7, 2014
- Cavium, Inc.
- Craig Barner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
LOW LATENCY INTER-CHIP COMMUNICATION MECHANISM IN A MULTI-CHIP PROC...
- Publication number 20230229595
- Publication date Jul 20, 2023
- Marvell Asia Pte, Ltd.
- Craig BARNER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LATENCY INTER-CHIP COMMUNICATION MECHANISM IN A MULTI-CHIP PROC...
- Publication number 20210374057
- Publication date Dec 2, 2021
- Marvell Asia Pte, Ltd.
- Craig BARNER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LATENCY INTER-CHIP COMMUNICATION MECHANISM IN MULTI-CHIP PROCES...
- Publication number 20200250088
- Publication date Aug 6, 2020
- Cavium LLC
- Craig Barner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Word Boundary Lock
- Publication number 20150016574
- Publication date Jan 15, 2015
- Cavium, Inc.
- Craig Barner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Word Boundary Lock
- Publication number 20130101069
- Publication date Apr 25, 2013
- Cavium, Inc.
- Craig Barner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Polarity Detection
- Publication number 20130101076
- Publication date Apr 25, 2013
- Cavium, Inc.
- Craig Barner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Bit Error Rate Impact Reduction
- Publication number 20130104012
- Publication date Apr 25, 2013
- Cavium, Inc.
- Craig Barner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MICROCODE AUTHENTICATION
- Publication number 20120216050
- Publication date Aug 23, 2012
- Cavium, Inc.
- Craig Barner
- G06 - COMPUTING CALCULATING COUNTING

Craig Barner

Person

Patents Grantslast 30 patents

Low latency inter-chip communication mechanism in a multi-chip proc...

Low latency inter-chip communication mechanism in a multi-chip proc...

Low latency inter-chip communication mechanism in multi-chip proces...

Bit error rate impact reduction

Word boundary lock

Word boundary lock

Patents Applicationslast 30 patents

LOW LATENCY INTER-CHIP COMMUNICATION MECHANISM IN A MULTI-CHIP PROC...

LOW LATENCY INTER-CHIP COMMUNICATION MECHANISM IN A MULTI-CHIP PROC...

LOW LATENCY INTER-CHIP COMMUNICATION MECHANISM IN MULTI-CHIP PROCES...

Word Boundary Lock

Word Boundary Lock

Polarity Detection

Bit Error Rate Impact Reduction

MICROCODE AUTHENTICATION