Cynthia ALLISON

Person

Madison, AL, US

People

Patents Grantslast 30 patents

Information Patent Grant
Data structures for efficient tiled rendering
- Patent number 10,489,875
- Issue date Nov 26, 2019
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-pass rendering in a screen space pipeline
- Patent number 10,430,989
- Issue date Oct 1, 2019
- NVIDIA Corporation
- Ziyad Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
State handling in a tiled architecture
- Patent number 10,282,803
- Issue date May 7, 2019
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-pass rendering in a screen space pipeline
- Patent number 10,147,222
- Issue date Dec 4, 2018
- NVIDIA Corporation
- Ziyad Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for managing graphics processing resources in a tile-bas...
- Patent number 10,083,036
- Issue date Sep 25, 2018
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed tiled caching
- Patent number 10,032,243
- Issue date Jul 24, 2018
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heuristics for improving performance in a tile based architecture
- Patent number 9,792,122
- Issue date Oct 17, 2017
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for managing graphics processing resources in a tile-bas...
- Patent number 9,639,366
- Issue date May 2, 2017
- NVIDIA Corporation
- Karim M. Abdalla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heuristics for improving performance in a tile-based architecture
- Patent number 9,542,189
- Issue date Jan 10, 2017
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed tiled caching
- Patent number 9,483,270
- Issue date Nov 1, 2016
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for managing graphics processing resources in a tile-bas...
- Patent number 9,448,804
- Issue date Sep 20, 2016
- NVIDIA Corporation
- Ziyad S. Hakura
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Techniques for adaptively generating bounding boxes
- Patent number 9,342,311
- Issue date May 17, 2016
- NVIDIA Corporation
- Ziyad S. Hakura
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Data structures for efficient tiled rendering
- Patent number 9,336,002
- Issue date May 10, 2016
- NVIDIA Corporation
- Ziyad S. Hakura
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Redistribution of generated geometric primitives
- Patent number 8,917,271
- Issue date Dec 23, 2014
- NVIDIA Corporation
- Johnny S. Rhoades
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware-managed virtual buffers using a shared memory for load dis...
- Patent number 8,760,460
- Issue date Jun 24, 2014
- NVIDIA Corporation
- Emmett M. Kilgariff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Primitive re-ordering between world-space and screen-space pipeline...
- Patent number 8,704,826
- Issue date Apr 22, 2014
- NVIDIA Corporation
- Ziyad S. Hakura
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Peer-to-peer parallel processing graphics accelerator
- Patent number 6,046,752
- Issue date Apr 4, 2000
- Intergraph Corporation
- Dale Kirkland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Peer-to-peer parallel processing graphics accelerator
- Patent number 5,917,502
- Issue date Jun 29, 1999
- Intergraph Corporation
- Dale L. Kirkland
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTI-PASS RENDERING IN A SCREEN SPACE PIPELINE
- Publication number 20170148203
- Publication date May 25, 2017
- NVIDIA Corporation
- Ziyad HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PASS RENDERING IN A SCREEN SPACE PIPELINE
- Publication number 20170148204
- Publication date May 25, 2017
- NVIDIA Corporation
- Ziyad HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HEURISTICS FOR IMPROVING PERFORMANCE IN A TILE-BASED ARCHITECTURE
- Publication number 20150097845
- Publication date Apr 9, 2015
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRIMITIVE RE-ORDERING BETWEEN WORLD-SPACE AND SCREEN-SPACE PIPELINE...
- Publication number 20140118381
- Publication date May 1, 2014
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR MANAGINGGRAPHICS PROCESSING RESOURCES IN A TILE-BASE...
- Publication number 20140118373
- Publication date May 1, 2014
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED TILED CACHING
- Publication number 20140118361
- Publication date May 1, 2014
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED TILED CACHING
- Publication number 20140118364
- Publication date May 1, 2014
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR MANAGING GRAPHICS PROCESSING RESOURCES IN A TILE-BAS...
- Publication number 20140118375
- Publication date May 1, 2014
- NVIDIA Corporation
- Karim M. ABDALLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HEURISTICS FOR IMPROVING PERFORMANCE IN A TILE BASED ARCHITECTURE
- Publication number 20140118376
- Publication date May 1, 2014
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATE HANDLING IN A TILED ARCHITECTURE
- Publication number 20140118380
- Publication date May 1, 2014
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR MANAGINGGRAPHICS PROCESSING RESOURCES IN A TILE-BASE...
- Publication number 20140118374
- Publication date May 1, 2014
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIME SLICE PROCESSING OF TESSELLATION AND GEOMETRY SHADERS
- Publication number 20130038620
- Publication date Feb 14, 2013
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING

Cynthia ALLISON

Person

Patents Grantslast 30 patents

Data structures for efficient tiled rendering

Multi-pass rendering in a screen space pipeline

State handling in a tiled architecture

Multi-pass rendering in a screen space pipeline

Techniques for managing graphics processing resources in a tile-bas...

Distributed tiled caching

Heuristics for improving performance in a tile based architecture

Techniques for managing graphics processing resources in a tile-bas...

Heuristics for improving performance in a tile-based architecture

Distributed tiled caching

Techniques for managing graphics processing resources in a tile-bas...

Techniques for adaptively generating bounding boxes

Data structures for efficient tiled rendering

Redistribution of generated geometric primitives

Hardware-managed virtual buffers using a shared memory for load dis...

Primitive re-ordering between world-space and screen-space pipeline...

Peer-to-peer parallel processing graphics accelerator

Peer-to-peer parallel processing graphics accelerator

Patents Applicationslast 30 patents

MULTI-PASS RENDERING IN A SCREEN SPACE PIPELINE

MULTI-PASS RENDERING IN A SCREEN SPACE PIPELINE

HEURISTICS FOR IMPROVING PERFORMANCE IN A TILE-BASED ARCHITECTURE

PRIMITIVE RE-ORDERING BETWEEN WORLD-SPACE AND SCREEN-SPACE PIPELINE...

TECHNIQUES FOR MANAGINGGRAPHICS PROCESSING RESOURCES IN A TILE-BASE...

DISTRIBUTED TILED CACHING

DISTRIBUTED TILED CACHING

TECHNIQUES FOR MANAGING GRAPHICS PROCESSING RESOURCES IN A TILE-BAS...

HEURISTICS FOR IMPROVING PERFORMANCE IN A TILE BASED ARCHITECTURE

STATE HANDLING IN A TILED ARCHITECTURE

TECHNIQUES FOR MANAGINGGRAPHICS PROCESSING RESOURCES IN A TILE-BASE...

TIME SLICE PROCESSING OF TESSELLATION AND GEOMETRY SHADERS