Daisuke Kondo

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Kawasaki-shi, JP

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Patents Grantslast 30 patents

Information Patent Grant
Method for designing a semiconductor integrated circuit layout capa...
- Patent number 7,844,934
- Issue date Nov 30, 2010
- Renesas Electronics Corporation
- Yusaku Ono
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method for designing semiconductor integrated circuit layout
- Publication number 20070124714
- Publication date May 31, 2007
- Renesas Technology Corp.
- Yusaku Ono
- G06 - COMPUTING CALCULATING COUNTING