Dale W. Martin

Person

Essex Junction, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Flattened substrate surface for substrate bonding
- Patent number 9,355,936
- Issue date May 31, 2016
- GLOBALFOUNDRIES Inc.
- Edward C. Cooney
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High linearity SOI wafer for low-distortion circuit applications
- Patent number 9,165,819
- Issue date Oct 20, 2015
- GLOBALFOUNDRIES Inc.
- Alan B. Botula
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High linearity SOI wafer for low-distortion circuit applications
- Patent number 8,951,896
- Issue date Feb 10, 2015
- International Business Machines Corporation
- Alan B. Botula
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flattened substrate surface for substrate bonding
- Patent number 8,778,737
- Issue date Jul 15, 2014
- International Business Machines Corporation
- Edward C. Cooney
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fine tuning highly resistive substrate resistivity and structures t...
- Patent number 8,679,863
- Issue date Mar 25, 2014
- International Business Machines Corporation
- Jeffrey P. Gambino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High resistivity SOI base wafer using thermally annealed substrate
- Patent number 7,883,990
- Issue date Feb 8, 2011
- International Business Machines Corporation
- Max Levy
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Multi-layer spacer with inhibited recess/undercut and method for fa...
- Patent number 7,446,007
- Issue date Nov 4, 2008
- International Business Machines Corporation
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate stacks
- Patent number 7,378,712
- Issue date May 27, 2008
- International Business Machines Corporation
- Dale W. Martin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating doped polysilicon lines
- Patent number 7,303,952
- Issue date Dec 4, 2007
- International Business Machines Corporation
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolated fully depleted silicon-on-insulator regions by selective etch
- Patent number 7,190,007
- Issue date Mar 13, 2007
- International Business Machines Corporation
- Matthew J. Breitwisch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate stacks
- Patent number 7,157,341
- Issue date Jan 2, 2007
- International Business Machines Corporation
- Dale W. Martin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contact areas for sidewall image transfer formed condu...
- Patent number 6,949,458
- Issue date Sep 27, 2005
- International Business Machines Corporation
- Edward W. Conrad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to define and tailor process limited lithographic features u...
- Patent number 6,610,607
- Issue date Aug 26, 2003
- International Business Machines Corporation
- Douglas S. Armbrust
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contact areas for sidewall image transfer formed condu...
- Patent number 6,566,759
- Issue date May 20, 2003
- International Business Machines Corporation
- Edward W. Conrad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned non-volatile random access memory cell and process to...
- Patent number 6,525,371
- Issue date Feb 25, 2003
- International Business Machines Corporation
- Jeffrey B. Johnson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduction of reverse short channel effects by implantation of neutr...
- Patent number 6,486,510
- Issue date Nov 26, 2002
- International Business Machines Corporation
- Jeffrey Scott Brown
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduction of reverse short channel effects by deep implantation of...
- Patent number 6,352,912
- Issue date Mar 5, 2002
- International Business Machines Corporation
- Jeffrey Scott Brown
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a point on a floating gate for electron injection
- Patent number 6,294,429
- Issue date Sep 25, 2001
- International Business Machines Corporation
- Chung H. Lam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple thickness of gate oxide
- Patent number 6,258,673
- Issue date Jul 10, 2001
- International Business Machines Corporation
- Kevin M. Houlihan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for dual sidewall oxidation in high density, high performanc...
- Patent number 6,197,632
- Issue date Mar 6, 2001
- International Business Machines Corporation
- Gary B. Bronner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of deuterated materials in semiconductor processing
- Patent number 5,972,765
- Issue date Oct 26, 1999
- International Business Machines Corporation
- William F. Clark
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for providing multiple gate oxide thicknesses on the same wafer
- Patent number 5,926,708
- Issue date Jul 20, 1999
- International Business Machines Corp.
- Dale W. Martin
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
HIGH LINEARITY SOI WAFER FOR LOW-DISTORTION CIRCUIT APPLICATIONS
- Publication number 20150072504
- Publication date Mar 12, 2015
- International Business Machines Corporation
- ALAN B. BOTULA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH LINEARITY SOI WAFER FOR LOW-DISTORTION CIRCUIT APPLICATIONS
- Publication number 20150004778
- Publication date Jan 1, 2015
- International Business Machines Corporation
- ALAN B. BOTULA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING
- Publication number 20140209908
- Publication date Jul 31, 2014
- International Business Machines Corporation
- Edward C. Cooney
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINE TUNING HIGHLY RESISTIVE SUBSTRATE RESISTIVITY AND STRUCTURES T...
- Publication number 20130244348
- Publication date Sep 19, 2013
- International Business Machines Corporation
- Jeffrey P. GAMBINO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING
- Publication number 20130105981
- Publication date May 2, 2013
- International Business Machines Corporation
- Edward C. Cooney
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH RESISTIVITY SOI BASE WAFER USING THERMALLY ANNEALED SUBSTRATE
- Publication number 20090110898
- Publication date Apr 30, 2009
- International Business Machines Corporation
- Max Levy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LAYER SPACER WITH INHIBITED RECESS/UNDERCUT AND METHOD FOR FA...
- Publication number 20080116493
- Publication date May 22, 2008
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING DOPED POLYSILICON LINES
- Publication number 20070287275
- Publication date Dec 13, 2007
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE STACKS
- Publication number 20070194385
- Publication date Aug 23, 2007
- Dale W. Martin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ISOLATED FULLY DEPLETED SILICON-ON-INSULATOR REGIONS BY SELECTIVE ETCH
- Publication number 20070128776
- Publication date Jun 7, 2007
- International Business Machines Corporation
- Matthew J. Breitwisch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL SILICIDE PROCESS TO IMPROVE DEVICE PERFORMANCE
- Publication number 20060163670
- Publication date Jul 27, 2006
- International Business Machines Corporation
- John J. Ellis-Monaghan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE STACKS
- Publication number 20060073688
- Publication date Apr 6, 2006
- International Business Machines Corporation
- Dale W. Martin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING DOPED POLYSILICON LINES
- Publication number 20060073689
- Publication date Apr 6, 2006
- International Business Machines Corporation
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Isolated fully depleted silicon-on-insulator regions by selective etch
- Publication number 20060027889
- Publication date Feb 9, 2006
- International Business Machines Corporation
- Matthew J. Breitwisch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-aligned contact areas for sidewall image transfer formed condu...
- Publication number 20030115750
- Publication date Jun 26, 2003
- International Business Machines Corporation
- Edward W. Conrad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED NON-VOLATILE RANDOM ACCESS MEMORY CELL AND PROCESS TO...
- Publication number 20020109179
- Publication date Aug 15, 2002
- JEFFREY B. JOHNSON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Reduction of reverse short channel effects by implantation of neutr...
- Publication number 20020063294
- Publication date May 30, 2002
- International Business Machines
- Jeffrey Scott Brown
- H01 - BASIC ELECTRIC ELEMENTS

Dale W. Martin

Person

Patents Grantslast 30 patents

Flattened substrate surface for substrate bonding

High linearity SOI wafer for low-distortion circuit applications

High linearity SOI wafer for low-distortion circuit applications

Flattened substrate surface for substrate bonding

Fine tuning highly resistive substrate resistivity and structures t...

High resistivity SOI base wafer using thermally annealed substrate

Multi-layer spacer with inhibited recess/undercut and method for fa...

Gate stacks

Method for fabricating doped polysilicon lines

Isolated fully depleted silicon-on-insulator regions by selective etch

Gate stacks

Self-aligned contact areas for sidewall image transfer formed condu...

Method to define and tailor process limited lithographic features u...

Self-aligned contact areas for sidewall image transfer formed condu...

Self-aligned non-volatile random access memory cell and process to...

Reduction of reverse short channel effects by implantation of neutr...

Reduction of reverse short channel effects by deep implantation of...

Method of forming a point on a floating gate for electron injection

Multiple thickness of gate oxide

Method for dual sidewall oxidation in high density, high performanc...

Use of deuterated materials in semiconductor processing

Method for providing multiple gate oxide thicknesses on the same wafer

Patents Applicationslast 30 patents

HIGH LINEARITY SOI WAFER FOR LOW-DISTORTION CIRCUIT APPLICATIONS

HIGH LINEARITY SOI WAFER FOR LOW-DISTORTION CIRCUIT APPLICATIONS

FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING

FINE TUNING HIGHLY RESISTIVE SUBSTRATE RESISTIVITY AND STRUCTURES T...

FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING

HIGH RESISTIVITY SOI BASE WAFER USING THERMALLY ANNEALED SUBSTRATE

MULTI-LAYER SPACER WITH INHIBITED RECESS/UNDERCUT AND METHOD FOR FA...

METHOD FOR FABRICATING DOPED POLYSILICON LINES

GATE STACKS

ISOLATED FULLY DEPLETED SILICON-ON-INSULATOR REGIONS BY SELECTIVE ETCH

DUAL SILICIDE PROCESS TO IMPROVE DEVICE PERFORMANCE

GATE STACKS

METHOD FOR FABRICATING DOPED POLYSILICON LINES

Isolated fully depleted silicon-on-insulator regions by selective etch

Self-aligned contact areas for sidewall image transfer formed condu...

SELF-ALIGNED NON-VOLATILE RANDOM ACCESS MEMORY CELL AND PROCESS TO...

Reduction of reverse short channel effects by implantation of neutr...