Dan Hillman

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Power managers for an integrated circuit
- Patent number 11,362,645
- Issue date Jun 14, 2022
- Mosaid Technologies Incorporated
- Barry Alan Hoberman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power managers for an integrated circuit
- Patent number 10,749,506
- Issue date Aug 18, 2020
- Conversant Intellectual Property Management Inc.
- Barry Alan Hoberman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with a plurality of memory banks where each memory ba...
- Patent number 10,628,316
- Issue date Apr 21, 2020
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with a dual Y-multiplexer structure for performing tw...
- Patent number 10,460,781
- Issue date Oct 29, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory instruction pipeline with a pre-read stage for a write opera...
- Patent number 10,446,210
- Issue date Oct 15, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of flushing the contents of a dynamic redundancy register to...
- Patent number 10,437,723
- Issue date Oct 8, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of processing incomplete memory operations in a memory devic...
- Patent number 10,437,491
- Issue date Oct 8, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of reading data from a memory device using multiple levels o...
- Patent number 10,424,393
- Issue date Sep 24, 2019
- Spin Memory, Inc.
- Mourad El Baraji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device using levels of dynamic redundancy registers for writ...
- Patent number 10,366,775
- Issue date Jul 30, 2019
- Spin Memory, Inc.
- Mourad El Baraji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device with dynamic redundancy registers
- Patent number 10,366,774
- Issue date Jul 30, 2019
- Spin Memory, Inc.
- Mourad El Baraji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of writing contents in memory during a power up sequence usi...
- Patent number 10,360,964
- Issue date Jul 23, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power managers for an integrated circuit
- Patent number 10,243,542
- Issue date Mar 26, 2019
- Conversant Intellectual Property Management Inc.
- Barry Alan Hoberman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power managers for an integrated circuit
- Patent number 10,200,015
- Issue date Feb 5, 2019
- Conversant Intellectual Property Management Inc.
- Barry Alan Hoberman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory instruction pipeline with an additional write stage in a mem...
- Patent number 10,192,601
- Issue date Jan 29, 2019
- SPIN TRANSFER TECHNOLOGIES, INC.
- Neal Berger
- G11 - INFORMATION STORAGE
Information Patent Grant
Smart cache design to prevent overflow for a memory device with a d...
- Patent number 10,192,602
- Issue date Jan 29, 2019
- SPIN TRANSFER TECHNOLOGIES, INC.
- Neal Berger
- G11 - INFORMATION STORAGE
Information Patent Grant
Low leakage and data retention circuitry
- Patent number 9,722,605
- Issue date Aug 1, 2017
- Conversant Intellectual Property Management Inc.
- Barry A. Hoberman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power managers for an integrated circuit
- Patent number 9,660,616
- Issue date May 23, 2017
- Conversant Intellectual Property Management Inc.
- Barry Alan Hoberman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low leakage and data retention circuitry
- Patent number 9,350,349
- Issue date May 24, 2016
- Conversant Intellectual Property Management Inc.
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Grant
Power managers for an integrated circuit
- Patent number 9,166,412
- Issue date Oct 20, 2015
- Conversant Intellectual Property Management Inc.
- Barry Alan Hoberman
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Low leakage and data retention circuitry
- Patent number 8,854,077
- Issue date Oct 7, 2014
- Conversant Intellectual Property Management Inc.
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Grant
Power managers for an integrated circuit
- Patent number 8,782,590
- Issue date Jul 15, 2014
- Conversant Intellectual Property Management Inc.
- Barry Alan Hoberman
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Power managers for an integrated circuit
- Patent number 8,762,923
- Issue date Jun 24, 2014
- Conversant Intellectual Property Management Inc.
- Barry Alan Hoberman
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Low leakage and data retention circuitry
- Patent number 8,253,438
- Issue date Aug 28, 2012
- MOSAID Technologies Incorporated
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with signal bus formed by cell abutment of logic...
- Patent number 8,026,738
- Issue date Sep 27, 2011
- Mosaid Technologies Incorporated
- Daniel L. Hillman
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Power managers for an integrated circuit
- Patent number 7,996,811
- Issue date Aug 9, 2011
- MOSAID Technologies Incorporated
- Barry Alan Hoberman
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Power managers for an integrated circuit
- Patent number 7,945,885
- Issue date May 17, 2011
- MOSAID Technologies Incorporated
- Barry Alan Hoberman
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Low leakage and data retention circuitry
- Patent number 7,940,081
- Issue date May 10, 2011
- MOSAID Technologies Incorporated
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Grant
Low leakage and data retention circuitry
- Patent number 7,592,837
- Issue date Sep 22, 2009
- MOSAID Technologies Corporation
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for glitch correction
- Patent number 7,541,880
- Issue date Jun 2, 2009
- MOSAID Technologies Corporation
- Brian Jeffrey Galloway
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit with signal bus formed by cell abutment of logic...
- Patent number 7,508,256
- Issue date Mar 24, 2009
- MOSAID Technologies Corporation
- Daniel L. Hillman
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
POWER MANAGERS FOR AN INTEGRATED CIRCUIT
- Publication number 20210036689
- Publication date Feb 4, 2021
- Conversant Intellectual Property Management Inc.
- Barry Alan HOBERMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER MANAGERS FOR AN INTEGRATED CIRCUIT
- Publication number 20190173453
- Publication date Jun 6, 2019
- Conversant Intellectual Property Management Inc.
- Barry Alan HOBERMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF WRITING CONTENTS IN MEMORY DURING A POWER UP SEQUENCE USI...
- Publication number 20180122447
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY INSTRUCTION PIPELINE WITH A PRE-READ STAGE FOR A WRITE OPERA...
- Publication number 20180122448
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH A PLURALITY OF MEMORY BANKS WHERE EACH MEMORY BA...
- Publication number 20180121361
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF FLUSHING THE CONTENTS OF A DYNAMIC REDUNDANCY REGISTER TO...
- Publication number 20180121355
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY INSTRUCTION PIPELINE WITH AN ADDITIONAL WRITE STAGE IN A MEM...
- Publication number 20180122449
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH A DUAL Y-MULTIPLEXER STRUCTURE FOR PERFORMING TW...
- Publication number 20180122446
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
SMART CACHE DESIGN TO PREVENT OVERFLOW FOR A MEMORY DEVICE WITH A D...
- Publication number 20180122450
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF PROCESSING INCOMPLETED MEMORY OPERATIONS IN A MEMORY DEVI...
- Publication number 20180121117
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF READING DATA FROM A MEMORY DEVICE USING DYNAMIC REDUNDANC...
- Publication number 20180114589
- Publication date Apr 26, 2018
- Spin Transfer Technologies, Inc.
- Mourad EL BARAJI
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE USING DYNAMIC REDUNDANCY REGISTERS
- Publication number 20180114590
- Publication date Apr 26, 2018
- Spin Transfer Technologies, Inc.
- Mourad EL BARAJI
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE WITH DYNAMIC REDUNDANCY REGISTERS
- Publication number 20180090226
- Publication date Mar 29, 2018
- Spin Transfer Technologies, Inc.
- Mourad EL BARAJI
- G11 - INFORMATION STORAGE
Information Patent Application
POWER MANAGERS FOR AN INTEGRATED CIRCUIT
- Publication number 20170288649
- Publication date Oct 5, 2017
- Conversant Intellectual Property Management Inc.
- Barry Alan HOBERMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
- Publication number 20160315615
- Publication date Oct 27, 2016
- Conversant Intellectual Property Management Inc.
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Application
POWER MANAGERS FOR AN INTEGRATED CIRCUIT
- Publication number 20160087608
- Publication date Mar 24, 2016
- Conversant Intellectual Property Management Inc.
- Barry Alan HOBERMAN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low Leakage and Data Retention Circuitry
- Publication number 20140375354
- Publication date Dec 25, 2014
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Application
POWER MANAGERS FOR AN INTEGRATED CIRCUIT
- Publication number 20140333134
- Publication date Nov 13, 2014
- Barry Alan Hoberman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
- Publication number 20130027125
- Publication date Jan 31, 2013
- Barry A. Hoberman
- G11 - INFORMATION STORAGE
Information Patent Application
Power Managers for an Integrated Circuit
- Publication number 20120256485
- Publication date Oct 11, 2012
- Barry Alan Hoberman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power Managers for an Integrated Circuit
- Publication number 20120043812
- Publication date Feb 23, 2012
- Barry Alan Hoberman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Intermediate language accelerator chip
- Publication number 20120032965
- Publication date Feb 9, 2012
- Mukesh K. Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Intermediate Language Accelerator Chip
- Publication number 20120019549
- Publication date Jan 26, 2012
- Mukesh K. Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Intermediate Language Accelerator Chip
- Publication number 20120023310
- Publication date Jan 26, 2012
- Mukesh K. Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Intermediate Language Accelerator Chip
- Publication number 20120001926
- Publication date Jan 5, 2012
- Mukesh K. Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low Leakage and Data Retention Circuitry
- Publication number 20110260785
- Publication date Oct 27, 2011
- MOSAID TECHNOLOGIES INCORPORATED
- Barry A. Hoberman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
- Publication number 20100060319
- Publication date Mar 11, 2010
- MOSAID Technologies Corporation
- Barry A. Hoberman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
POWER MANAGERS FOR AN INTEGRATED CIRCUIT
- Publication number 20090152948
- Publication date Jun 18, 2009
- MOSAID TECHNOLOGIES CORPORATION
- Barry Alan HOBERMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH SIGNAL BUS FORMED BY CELL ABUTMENT OF LOGIC...
- Publication number 20090140800
- Publication date Jun 4, 2009
- MOSAID TECHNOLOGIES CORPORATION
- Daniel L. HILLMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low leakage and data retention circuitry
- Publication number 20090027080
- Publication date Jan 29, 2009
- MOSAID Technologies, Inc.
- Barry A. Hoberman
- H03 - BASIC ELECTRONIC CIRCUITRY

Dan Hillman

Person

Patents Grantslast 30 patents

Power managers for an integrated circuit

Power managers for an integrated circuit

Memory device with a plurality of memory banks where each memory ba...

Memory device with a dual Y-multiplexer structure for performing tw...

Memory instruction pipeline with a pre-read stage for a write opera...

Method of flushing the contents of a dynamic redundancy register to...

Method of processing incomplete memory operations in a memory devic...

Method of reading data from a memory device using multiple levels o...

Memory device using levels of dynamic redundancy registers for writ...

Device with dynamic redundancy registers

Method of writing contents in memory during a power up sequence usi...

Power managers for an integrated circuit

Power managers for an integrated circuit

Memory instruction pipeline with an additional write stage in a mem...

Smart cache design to prevent overflow for a memory device with a d...

Low leakage and data retention circuitry

Power managers for an integrated circuit

Low leakage and data retention circuitry

Power managers for an integrated circuit

Low leakage and data retention circuitry

Power managers for an integrated circuit

Power managers for an integrated circuit

Low leakage and data retention circuitry

Integrated circuit with signal bus formed by cell abutment of logic...

Power managers for an integrated circuit

Power managers for an integrated circuit

Low leakage and data retention circuitry

Low leakage and data retention circuitry

Circuit and method for glitch correction

Integrated circuit with signal bus formed by cell abutment of logic...

Patents Applicationslast 30 patents

POWER MANAGERS FOR AN INTEGRATED CIRCUIT

POWER MANAGERS FOR AN INTEGRATED CIRCUIT

METHOD OF WRITING CONTENTS IN MEMORY DURING A POWER UP SEQUENCE USI...

MEMORY INSTRUCTION PIPELINE WITH A PRE-READ STAGE FOR A WRITE OPERA...

MEMORY DEVICE WITH A PLURALITY OF MEMORY BANKS WHERE EACH MEMORY BA...

METHOD OF FLUSHING THE CONTENTS OF A DYNAMIC REDUNDANCY REGISTER TO...

MEMORY INSTRUCTION PIPELINE WITH AN ADDITIONAL WRITE STAGE IN A MEM...

MEMORY DEVICE WITH A DUAL Y-MULTIPLEXER STRUCTURE FOR PERFORMING TW...

SMART CACHE DESIGN TO PREVENT OVERFLOW FOR A MEMORY DEVICE WITH A D...

METHOD OF PROCESSING INCOMPLETED MEMORY OPERATIONS IN A MEMORY DEVI...

METHOD OF READING DATA FROM A MEMORY DEVICE USING DYNAMIC REDUNDANC...

MEMORY DEVICE USING DYNAMIC REDUNDANCY REGISTERS

DEVICE WITH DYNAMIC REDUNDANCY REGISTERS

POWER MANAGERS FOR AN INTEGRATED CIRCUIT

LOW LEAKAGE AND DATA RETENTION CIRCUITRY

POWER MANAGERS FOR AN INTEGRATED CIRCUIT

Low Leakage and Data Retention Circuitry

POWER MANAGERS FOR AN INTEGRATED CIRCUIT

LOW LEAKAGE AND DATA RETENTION CIRCUITRY

Power Managers for an Integrated Circuit

Power Managers for an Integrated Circuit

Intermediate language accelerator chip

Intermediate Language Accelerator Chip

Intermediate Language Accelerator Chip

Intermediate Language Accelerator Chip

Low Leakage and Data Retention Circuitry

LOW LEAKAGE AND DATA RETENTION CIRCUITRY

POWER MANAGERS FOR AN INTEGRATED CIRCUIT

INTEGRATED CIRCUIT WITH SIGNAL BUS FORMED BY CELL ABUTMENT OF LOGIC...

Low leakage and data retention circuitry