Dana L. How

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Programmable integrated circuits with in-operation reconfiguration...
- Patent number 10,591,544
- Issue date Mar 17, 2020
- Altera Corporation
- Dana How
- G01 - MEASURING TESTING
Information Patent Grant
Techniques for signal skew compensation
- Patent number 10,523,224
- Issue date Dec 31, 2019
- Altera Corporation
- David Mendel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable circuit having multiple sectors
- Patent number 10,523,207
- Issue date Dec 31, 2019
- Altera Corporation
- Dana How
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Network-on-chip with fixed and configurable functions
- Patent number 10,367,745
- Issue date Jul 30, 2019
- Altera Corporation
- Dana How
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable logic device with integrated network-on-chip
- Patent number 10,367,756
- Issue date Jul 30, 2019
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for signal skew compensation
- Patent number 10,333,535
- Issue date Jun 25, 2019
- Altera Corporation
- David Mendel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuits with embedded double-clocked components
- Patent number 10,210,919
- Issue date Feb 19, 2019
- Altera Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mixed redundancy scheme for inter-die interconnects in a multichip...
- Patent number 10,082,541
- Issue date Sep 25, 2018
- Altera Corporation
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for a low hold-time sequential input stage
- Patent number 10,044,344
- Issue date Aug 7, 2018
- Altera Corporation
- Dana How
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mixed redundancy scheme for inter-die interconnects in a multichip...
- Patent number 10,031,182
- Issue date Jul 24, 2018
- Altera Corporation
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for clock alignment using pipeline stages
- Patent number 9,960,903
- Issue date May 1, 2018
- Altera Corporation
- Dana How
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuit design implementations in secure partitions of an integrate...
- Patent number 9,946,826
- Issue date Apr 17, 2018
- Altera Corporation
- Sean Atsatt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sector-based clock routing methods and apparatus
- Patent number 9,922,157
- Issue date Mar 20, 2018
- Altera Corporation
- Carl Ebeling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock grid for integrated circuit
- Patent number 9,843,332
- Issue date Dec 12, 2017
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for a low hold-time sequential input stage
- Patent number 9,806,696
- Issue date Oct 31, 2017
- Altera Corporation
- Dana How
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-stuffing multi-clock FIFO requiring no synchronizers
- Patent number 9,703,526
- Issue date Jul 11, 2017
- Altera Corporation
- Dana How
- G11 - INFORMATION STORAGE
Information Patent Grant
Level-sensitive two-phase single-wire latch controllers without con...
- Patent number 9,698,784
- Issue date Jul 4, 2017
- Altera Corporation
- Dana How
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System reset controller replacing individual asynchronous resets
- Patent number 9,685,957
- Issue date Jun 20, 2017
- Altera Corporation
- Dana How
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory controller for heterogeneous configurable integrated circuit
- Patent number 9,665,677
- Issue date May 30, 2017
- Agate Logic, Inc.
- Suresh Subramanian
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock grid for integrated circuit
- Patent number 9,660,630
- Issue date May 23, 2017
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable clock grid structures
- Patent number 9,606,573
- Issue date Mar 28, 2017
- Altera Corporation
- Carl Ebeling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple plane network-on-chip with master/slave inter-relationships
- Patent number 9,602,587
- Issue date Mar 21, 2017
- Altera Corporation
- Dana How
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for using scan storage circuits
- Patent number 9,588,176
- Issue date Mar 7, 2017
- Altera Corporation
- Michael Hutton
- G01 - MEASURING TESTING
Information Patent Grant
Network-on-chip with fixed and configurable functions
- Patent number 9,553,762
- Issue date Jan 24, 2017
- Altera Corporation
- Dana How
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems and methods for clock alignment using pipeline stages
- Patent number 9,501,092
- Issue date Nov 22, 2016
- Altera Corporation
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock grid for integrated circuit
- Patent number 9,503,057
- Issue date Nov 22, 2016
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with integrated network-on-chip
- Patent number 9,479,456
- Issue date Oct 25, 2016
- Altera Corporation
- Michael David Hutton
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock grid for integrated circuit
- Patent number 9,473,112
- Issue date Oct 18, 2016
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Level-sensitive two-phase single-wire latch controllers without con...
- Patent number 9,385,717
- Issue date Jul 5, 2016
- Altera Corporation
- Dana How
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Deterministic FIFO buffer
- Patent number 9,250,859
- Issue date Feb 2, 2016
- Altera Corporation
- David W. Mendel
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP
- Publication number 20220224656
- Publication date Jul 14, 2022
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable Circuit Having Multiple Sectors
- Publication number 20200136624
- Publication date Apr 30, 2020
- Altera Corporation
- Dana How
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
NETWORK-ON-CHIP WITH FIXED AND CONFIGURABLE FUNCTIONS
- Publication number 20190327176
- Publication date Oct 24, 2019
- Altera Corporation
- Dana How
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Techniques For Signal Skew Compensation
- Publication number 20190273504
- Publication date Sep 5, 2019
- Altera Corporation
- David Mendel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP
- Publication number 20190215280
- Publication date Jul 11, 2019
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE INTEGRATED CIRCUITS WITH IN-OPERATION RECONFIGURATION...
- Publication number 20190018063
- Publication date Jan 17, 2019
- Altera Corporation
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR A LOW HOLD-TIME SEQUENTIAL INPUT STAGE
- Publication number 20180069533
- Publication date Mar 8, 2018
- Altera Corporation
- Dana How
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Memory Controller For Heterogeneous Configurable Integrated Circuit
- Publication number 20170249412
- Publication date Aug 31, 2017
- Agate Logic Inc.
- Suresh Subramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable Logic Device With Integrated Network-On-Chip
- Publication number 20170041249
- Publication date Feb 9, 2017
- Altera Corporation
- Michael David Hutton
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MIXED REDUNDANCY SCHEME FOR INTER-DIE INTERCONNECTS IN A MULTICHIP...
- Publication number 20160363626
- Publication date Dec 15, 2016
- Altera Corporation
- Dana How
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUITS WITH EMBEDDED DOUBLE-CLOCKED COMPONENTS
- Publication number 20160358638
- Publication date Dec 8, 2016
- Altera Corporation
- Martin Langhammer
- G11 - INFORMATION STORAGE
Information Patent Application
SELF-STUFFING MULTI-CLOCK FIFO REQUIRING NO SYNCHRONIZERS
- Publication number 20160268005
- Publication date Sep 15, 2016
- Altera Corporation
- Dana How
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE CIRCUIT HAVING MULTIPLE SECTORS
- Publication number 20160049941
- Publication date Feb 18, 2016
- Altera Corporation
- Dana How
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTIPLE PLANE NETWORK-ON-CHIP WITH MASTER/SLAVE INTER-RELATIONSHIPS
- Publication number 20150381707
- Publication date Dec 31, 2015
- Altera Corporation
- Dana How
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System Reset Controller Replacing Individual Asynchronous Resets
- Publication number 20150295579
- Publication date Oct 15, 2015
- Altera Corporation
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Controller for Heterogeneous Configurable Integrated Circuit
- Publication number 20150269300
- Publication date Sep 24, 2015
- Agate Logic Inc.
- Suresh Subramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINISTIC FIFO BUFFER
- Publication number 20150205579
- Publication date Jul 23, 2015
- Altera Corporation
- David W. MENDEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP
- Publication number 20140126572
- Publication date May 8, 2014
- Altera Corporation
- Michael David Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method of Signal Processing Engines With Programmable Lo...
- Publication number 20100306429
- Publication date Dec 2, 2010
- AGATE LOGIC, INC.
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High-bandwidth interconnect network for an integrated circuit
- Publication number 20090073967
- Publication date Mar 19, 2009
- CSWITCH Corporation
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER FOR HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUITS
- Publication number 20090072856
- Publication date Mar 19, 2009
- Cswitch Corporation
- Suresh Subramaniam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUIT
- Publication number 20090072858
- Publication date Mar 19, 2009
- Cswitch Corporation
- Godfrey P. D'Souza
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Function block architecture for gate array
- Publication number 20030214324
- Publication date Nov 20, 2003
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for controlling and observing data in a logic...
- Publication number 20020073369
- Publication date Jun 13, 2002
- LightSpeed Semiconductor Corporation
- Dana How
- G01 - MEASURING TESTING

Dana L. How

Person

Patents Grantslast 30 patents

Programmable integrated circuits with in-operation reconfiguration...

Techniques for signal skew compensation

Programmable circuit having multiple sectors

Network-on-chip with fixed and configurable functions

Programmable logic device with integrated network-on-chip

Techniques for signal skew compensation

Integrated circuits with embedded double-clocked components

Mixed redundancy scheme for inter-die interconnects in a multichip...

Systems and methods for a low hold-time sequential input stage

Mixed redundancy scheme for inter-die interconnects in a multichip...

Systems and methods for clock alignment using pipeline stages

Circuit design implementations in secure partitions of an integrate...

Sector-based clock routing methods and apparatus

Clock grid for integrated circuit

Systems and methods for a low hold-time sequential input stage

Self-stuffing multi-clock FIFO requiring no synchronizers

Level-sensitive two-phase single-wire latch controllers without con...

System reset controller replacing individual asynchronous resets

Memory controller for heterogeneous configurable integrated circuit

Clock grid for integrated circuit

Configurable clock grid structures

Multiple plane network-on-chip with master/slave inter-relationships

Techniques for using scan storage circuits

Network-on-chip with fixed and configurable functions

Systems and methods for clock alignment using pipeline stages

Clock grid for integrated circuit

Programmable logic device with integrated network-on-chip

Clock grid for integrated circuit

Level-sensitive two-phase single-wire latch controllers without con...

Deterministic FIFO buffer

Patents Applicationslast 30 patents

PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP

Programmable Circuit Having Multiple Sectors

NETWORK-ON-CHIP WITH FIXED AND CONFIGURABLE FUNCTIONS

Techniques For Signal Skew Compensation

PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP

PROGRAMMABLE INTEGRATED CIRCUITS WITH IN-OPERATION RECONFIGURATION...

SYSTEMS AND METHODS FOR A LOW HOLD-TIME SEQUENTIAL INPUT STAGE

Memory Controller For Heterogeneous Configurable Integrated Circuit

Programmable Logic Device With Integrated Network-On-Chip

MIXED REDUNDANCY SCHEME FOR INTER-DIE INTERCONNECTS IN A MULTICHIP...

INTEGRATED CIRCUITS WITH EMBEDDED DOUBLE-CLOCKED COMPONENTS

SELF-STUFFING MULTI-CLOCK FIFO REQUIRING NO SYNCHRONIZERS

PROGRAMMABLE CIRCUIT HAVING MULTIPLE SECTORS

MULTIPLE PLANE NETWORK-ON-CHIP WITH MASTER/SLAVE INTER-RELATIONSHIPS

System Reset Controller Replacing Individual Asynchronous Resets

Memory Controller for Heterogeneous Configurable Integrated Circuit

DETERMINISTIC FIFO BUFFER

PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP

System and Method of Signal Processing Engines With Programmable Lo...

High-bandwidth interconnect network for an integrated circuit

MEMORY CONTROLLER FOR HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUITS

HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUIT

Function block architecture for gate array

Method and apparatus for controlling and observing data in a logic...