Daniel Chu

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatuses and methods for concurrently accessing multiple partiti...
- Patent number 11,768,603
- Issue date Sep 26, 2023
- Micron Technology, Inc.
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for concurrently accessing multiple partiti...
- Patent number 11,354,040
- Issue date Jun 7, 2022
- Micron Technology, Inc.
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual demarcation voltage sensing before writes
- Patent number 11,024,380
- Issue date Jun 1, 2021
- Intel Corporation
- Daniel Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for concurrently accessing multiple partiti...
- Patent number 10,719,237
- Issue date Jul 21, 2020
- Micron Technology, Inc.
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tailoring timing offsets during a programming pulse for a memory de...
- Patent number 10,553,286
- Issue date Feb 4, 2020
- Intel Corporation
- Koushik Banerjee
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual demarcation voltage sensing before writes
- Patent number 10,482,960
- Issue date Nov 19, 2019
- Intel Corporation
- Daniel Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for multi-level setback read for three dimensi...
- Patent number 10,438,659
- Issue date Oct 8, 2019
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Cell programming verification
- Patent number 10,325,652
- Issue date Jun 18, 2019
- Intel Corporation
- Daniel J. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase change memory with mask receiver
- Patent number 10,037,799
- Issue date Jul 31, 2018
- Intel Corporation
- Daniel J. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for multi-level setback read for three dimensi...
- Patent number 10,032,508
- Issue date Jul 24, 2018
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and systems for verifying cell programming in phase change...
- Patent number 9,747,977
- Issue date Aug 29, 2017
- Intel Corporation
- Daniel J. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase change memory with mask receiver
- Patent number 9,406,378
- Issue date Aug 2, 2016
- Intel Corporation
- Daniel J. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Mitigating read disturb in a cross-point memory
- Patent number 9,286,975
- Issue date Mar 15, 2016
- Intel Corporation
- Daniel J. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-disabling chip enable input
- Patent number 9,196,316
- Issue date Nov 24, 2015
- Intel Corporation
- Daniel Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase change memory mask
- Patent number 8,913,425
- Issue date Dec 16, 2014
- Intel Corporation
- Daniel J. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and method for shifting a voltage level
- Patent number 8,860,488
- Issue date Oct 14, 2014
- Micron Technology, Inc.
- Daniel Chu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-disabling chip enable input
- Patent number 8,630,107
- Issue date Jan 14, 2014
- Intel Corporation
- Daniel J. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual mode negative voltage switching
- Patent number 7,570,466
- Issue date Aug 4, 2009
- Intel Corporation
- Daniel Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Cascode protected negative voltage switching
- Patent number 7,382,591
- Issue date Jun 3, 2008
- Intel Corporation
- Bi Han
- G11 - INFORMATION STORAGE
Information Patent Grant
Selecting a bias for a level shifting device
- Patent number 7,317,346
- Issue date Jan 8, 2008
- Intel Corporation
- Daniel J. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Stress tolerant high voltage back-to-back switch
- Patent number 7,116,151
- Issue date Oct 3, 2006
- Intel Corporation
- Gerald J. Barkley
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE PARTITI...
- Publication number 20220261151
- Publication date Aug 18, 2022
- Micron Technology, Inc.
- RAJESH SUNDARAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO GENERATE & ADJUST PROGRAM CURRENT PULSES FOR CROSS-PO...
- Publication number 20210090652
- Publication date Mar 25, 2021
- Intel Corporation
- Kevin E. ARENDT
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE PARTITI...
- Publication number 20200341635
- Publication date Oct 29, 2020
- Micron Technology, Inc.
- RAJESH SUNDARAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL DEMARCATION VOLTAGE SENSING BEFORE WRITES
- Publication number 20200160908
- Publication date May 21, 2020
- Intel Corporation
- Daniel Chu
- G11 - INFORMATION STORAGE
Information Patent Application
TAILORING TIMING OFFSETS DURING A PROGRAMMING PULSE FOR A MEMORY DE...
- Publication number 20190043585
- Publication date Feb 7, 2019
- Intel Corporation
- Koushik Banerjee
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR MULTI-LEVEL SETBACK READ FOR THREE DIMENSI...
- Publication number 20190013071
- Publication date Jan 10, 2019
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR MULTI-LEVEL SETBACK READ FOR THREE DIMENSI...
- Publication number 20180190353
- Publication date Jul 5, 2018
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
CELL PROGRAMMING VERIFICATION
- Publication number 20180068720
- Publication date Mar 8, 2018
- Intel Corporation
- Daniel J. Chu
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL DEMARCATION VOLTAGE SENSING BEFORE WRITES
- Publication number 20170236580
- Publication date Aug 17, 2017
- Intel Corporation
- Daniel Chu
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE PARTITI...
- Publication number 20170199666
- Publication date Jul 13, 2017
- Micron Technology, Inc.
- RAJESH SUNDARAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE CHANGE MEMORY MASK
- Publication number 20170025171
- Publication date Jan 26, 2017
- Intel Corporation
- Daniel J. Chu
- G11 - INFORMATION STORAGE
Information Patent Application
MITIGATING READ DISTURB IN A CROSS-POINT MEMORY
- Publication number 20150262661
- Publication date Sep 17, 2015
- Intel Corporation
- DANIEL J. CHU
- G11 - INFORMATION STORAGE
Information Patent Application
PHASE CHANGE MEMORY MASK
- Publication number 20150085570
- Publication date Mar 26, 2015
- Intel Corporation
- Daniel J. Chu
- G11 - INFORMATION STORAGE
Information Patent Application
PHASE CHANGE MEMORY MASK
- Publication number 20140269043
- Publication date Sep 18, 2014
- DANIEL J. CHU
- G11 - INFORMATION STORAGE
Information Patent Application
CELL PROGRAMMING VERIFICATION
- Publication number 20140269045
- Publication date Sep 18, 2014
- Daniel J. Chu
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHOD FOR SHIFTING A VOLTAGE LEVEL
- Publication number 20140253209
- Publication date Sep 11, 2014
- Micron Technology, Inc.
- Daniel Chu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SELF-DISABLING CHIP ENABLE INPUT
- Publication number 20130272048
- Publication date Oct 17, 2013
- Daniel Chu
- G11 - INFORMATION STORAGE
Information Patent Application
SELF-DISABLING CHIP ENABLE INPUT
- Publication number 20130010517
- Publication date Jan 10, 2013
- Daniel J. Chu
- G11 - INFORMATION STORAGE
Information Patent Application
Cascode protected negative voltage switching
- Publication number 20060267414
- Publication date Nov 30, 2006
- Bi Han
- G11 - INFORMATION STORAGE
Information Patent Application
Bias selection
- Publication number 20060202740
- Publication date Sep 14, 2006
- Intel Corporation
- Daniel J. Chu
- G05 - CONTROLLING REGULATING
Information Patent Application
Dual mode negative voltage switching
- Publication number 20060197386
- Publication date Sep 7, 2006
- Daniel Chu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Stress tolerant high voltage back-to-back switch
- Publication number 20060001480
- Publication date Jan 5, 2006
- Gerald J. Barkley
- H03 - BASIC ELECTRONIC CIRCUITRY

Person

Patents Grantslast 30 patents

Apparatuses and methods for concurrently accessing multiple partiti...

Apparatuses and methods for concurrently accessing multiple partiti...

Dual demarcation voltage sensing before writes

Apparatuses and methods for concurrently accessing multiple partiti...

Tailoring timing offsets during a programming pulse for a memory de...

Dual demarcation voltage sensing before writes

Method and apparatus for multi-level setback read for three dimensi...

Cell programming verification

Phase change memory with mask receiver

Method and apparatus for multi-level setback read for three dimensi...

Methods and systems for verifying cell programming in phase change...

Phase change memory with mask receiver

Mitigating read disturb in a cross-point memory

Self-disabling chip enable input

Phase change memory mask

Apparatuses and method for shifting a voltage level

Self-disabling chip enable input

Dual mode negative voltage switching

Cascode protected negative voltage switching

Selecting a bias for a level shifting device

Stress tolerant high voltage back-to-back switch

Patents Applicationslast 30 patents

APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE PARTITI...

TECHNIQUES TO GENERATE & ADJUST PROGRAM CURRENT PULSES FOR CROSS-PO...

APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE PARTITI...

DUAL DEMARCATION VOLTAGE SENSING BEFORE WRITES

TAILORING TIMING OFFSETS DURING A PROGRAMMING PULSE FOR A MEMORY DE...

METHOD AND APPARATUS FOR MULTI-LEVEL SETBACK READ FOR THREE DIMENSI...

METHOD AND APPARATUS FOR MULTI-LEVEL SETBACK READ FOR THREE DIMENSI...

CELL PROGRAMMING VERIFICATION

DUAL DEMARCATION VOLTAGE SENSING BEFORE WRITES

APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE PARTITI...

PHASE CHANGE MEMORY MASK

MITIGATING READ DISTURB IN A CROSS-POINT MEMORY

PHASE CHANGE MEMORY MASK

PHASE CHANGE MEMORY MASK

CELL PROGRAMMING VERIFICATION

APPARATUSES AND METHOD FOR SHIFTING A VOLTAGE LEVEL

SELF-DISABLING CHIP ENABLE INPUT

SELF-DISABLING CHIP ENABLE INPUT

Cascode protected negative voltage switching

Bias selection

Dual mode negative voltage switching

Stress tolerant high voltage back-to-back switch