Daniel Eric Cress

Person

Starkville, MS, US

People

Patents Grantslast 30 patents

Information Patent Grant
Fifo bus-sizing, bus-matching datapath architecture
- Patent number 6,526,470
- Issue date Feb 25, 2003
- Cypress Semiconductor Corp.
- Daniel Eric Cress
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low voltage differential amplifier with high voltage protection
- Patent number 6,483,386
- Issue date Nov 19, 2002
- Cypress Semiconductor Corp.
- Daniel E. Cress
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bitline/dataline short scheme to improve fall-through timing in a m...
- Patent number 6,473,357
- Issue date Oct 29, 2002
- Cypress Semiconductor Corporation
- Junfei Fan
- G11 - INFORMATION STORAGE
Information Patent Grant
Flag generation scheme for FIFOs
- Patent number 6,442,657
- Issue date Aug 27, 2002
- Cypress Semiconductor Corporation
- Junfei Fan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for shorting retransmit recovery times utilizi...
- Patent number 6,366,979
- Issue date Apr 2, 2002
- Cypress Semiconductor Corp.
- Pidugu L. Narayana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Column redundancy scheme for bus-matching fifos
- Patent number 6,292,013
- Issue date Sep 18, 2001
- Cypress Semiconductor Corp.
- Daniel Eric Cress
- G11 - INFORMATION STORAGE
Information Patent Grant
Input buffer/level shifter
- Patent number 6,191,636
- Issue date Feb 20, 2001
- Cypress Semiconductor Corp.
- Daniel Eric Cress
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory cell
- Patent number 6,055,177
- Issue date Apr 25, 2000
- Cypress Semiconductor Corp.
- Pidugu L. Narayana
- G11 - INFORMATION STORAGE
Information Patent Grant
Staggered bitline precharge scheme
- Patent number 6,023,435
- Issue date Feb 8, 2000
- Cypress Semiconductor Corp.
- Pidugu L. Narayana
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed FIFO mark and retransmit scheme using latches and precharge
- Patent number 5,860,160
- Issue date Jan 12, 1999
- Cypress Semiconductor Corp.
- Pidugu L. Narayana
- G06 - COMPUTING CALCULATING COUNTING

Daniel Eric Cress

Person

Patents Grantslast 30 patents

Fifo bus-sizing, bus-matching datapath architecture

Low voltage differential amplifier with high voltage protection

Bitline/dataline short scheme to improve fall-through timing in a m...

Flag generation scheme for FIFOs

Apparatus and method for shorting retransmit recovery times utilizi...

Column redundancy scheme for bus-matching fifos

Input buffer/level shifter

Memory cell

Staggered bitline precharge scheme

High speed FIFO mark and retransmit scheme using latches and precharge