Daniel Froelich

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Test and measurement system for analyzing devices under test
- Patent number 12,216,558
- Issue date Feb 4, 2025
- Tektronix, Inc.
- Sam J. Strickling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method, and apparatus for SRIS mode selection for PCIE
- Patent number 12,135,581
- Issue date Nov 5, 2024
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods and devices for high-speed input/output margin tes...
- Patent number 12,117,486
- Issue date Oct 15, 2024
- Daniel S. Froelich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Margin test data tagging and predictive expected margins
- Patent number 12,061,232
- Issue date Aug 13, 2024
- Tektronix, Inc.
- Sam J. Strickling
- G01 - MEASURING TESTING
Information Patent Grant
Systems, methods, and devices for high-speed input/output margin te...
- Patent number 12,055,584
- Issue date Aug 6, 2024
- Tektronix, Inc.
- Daniel S. Froelich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cable condition indicator
- Patent number 12,055,603
- Issue date Aug 6, 2024
- Tektronix, Inc.
- Sam J. Strickling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems, methods and devices for high-speed input/output margin tes...
- Patent number 11,946,970
- Issue date Apr 2, 2024
- Tektronix, Inc.
- Daniel S. Froelich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods and devices for high-speed input/output margin tes...
- Patent number 11,940,483
- Issue date Mar 26, 2024
- Tektronix, Inc.
- Sam J. Strickling
- G01 - MEASURING TESTING
Information Patent Grant
Systems, methods, and devices for high-speed input/output margin te...
- Patent number 11,927,627
- Issue date Mar 12, 2024
- Tektronix, Inc.
- Daniel S. Froelich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test and measurement system for analyzing devices under test
- Patent number 11,782,809
- Issue date Oct 10, 2023
- Tektronix, Inc.
- Sam J. Strickling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect retimer enhancements
- Patent number 11,675,003
- Issue date Jun 13, 2023
- Intel Corporation
- Daniel S. Froelich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method, and apparatus for SRIS mode selection for PCIe
- Patent number 11,630,480
- Issue date Apr 18, 2023
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cross-talk generation in a multi-lane link during lane testing
- Patent number 11,327,861
- Issue date May 10, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adjustable retimer buffer
- Patent number 11,288,154
- Issue date Mar 29, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced pin count interface
- Patent number 11,163,717
- Issue date Nov 2, 2021
- Intel Corporation
- Michelle Jen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-band margin probing on an operational interconnect
- Patent number 11,157,350
- Issue date Oct 26, 2021
- Intel Corporation
- Daniel S. Froelich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adjustable retimer buffer
- Patent number 10,860,449
- Issue date Dec 8, 2020
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cross-talk generation in a multi-lane link during lane testing
- Patent number 10,853,212
- Issue date Dec 1, 2020
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced pin count interface
- Patent number 10,706,003
- Issue date Jul 7, 2020
- Intel Corporation
- Michelle Jen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-band margin probing on an operational interconnect
- Patent number 10,671,476
- Issue date Jun 2, 2020
- Intel Corporation
- Daniel S. Froelich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect retimer enhancements
- Patent number 10,534,034
- Issue date Jan 14, 2020
- Intel Corporation
- Daniel S. Froelich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced pin count interface
- Patent number 10,198,394
- Issue date Feb 5, 2019
- Intel Corporation
- Michelle Jen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Reducing precision timing measurement uncertainty
- Patent number 9,946,683
- Issue date Apr 17, 2018
- Intel Corporation
- Daniel Froelich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical interface for a serial interconnect
- Patent number 9,779,053
- Issue date Oct 3, 2017
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system for measuring latency in a physical un...
- Patent number 9,558,145
- Issue date Jan 31, 2017
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test logic for a serial interconnect
- Patent number 9,552,269
- Issue date Jan 24, 2017
- Intel Corporation
- Debendra Das Sharma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method, apparatus and system for measuring latency in a physical un...
- Patent number 9,262,347
- Issue date Feb 16, 2016
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incorporating an independent logic block in a system-on-a-chip
- Patent number 8,395,416
- Issue date Mar 12, 2013
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TEST AND MEASUREMENT SYSTEM FOR ANALYZING DEVICES UNDER TEST
- Publication number 20240004768
- Publication date Jan 4, 2024
- Tektronix, Inc.
- Sam J. Strickling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, METHOD, AND APPARATUS FOR SRIS MODE SELECTION FOR PCIE
- Publication number 20230022948
- Publication date Jan 26, 2023
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND DEVICES FOR HIGH-SPEED INPUT/OUTPUT MARGIN TE...
- Publication number 20220163587
- Publication date May 26, 2022
- Tektronix, Inc.
- Daniel S. Froelich
- G01 - MEASURING TESTING
Information Patent Application
SYSTEMS, METHODS, AND DEVICES FOR HIGH-SPEED INPUT/OUTPUT MARGIN TE...
- Publication number 20220163588
- Publication date May 26, 2022
- Tektronix, Inc.
- Daniel S. Froelich
- G01 - MEASURING TESTING
Information Patent Application
MARGIN TEST DATA TAGGING AND PREDICTIVE EXPECTED MARGINS
- Publication number 20220091185
- Publication date Mar 24, 2022
- Tektronix, Inc.
- Sam J. Strickling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CABLE CONDITION INDICATOR
- Publication number 20220034975
- Publication date Feb 3, 2022
- Tektronix, Inc.
- Sam J. Strickling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLEXER-ENABLED CABLES AND TEST FIXTURES
- Publication number 20220034967
- Publication date Feb 3, 2022
- Tektronix, Inc.
- Sam J. Strickling
- G01 - MEASURING TESTING
Information Patent Application
SYSTEMS, METHODS AND DEVICES FOR HIGH-SPEED INPUT/OUTPUT MARGIN TES...
- Publication number 20210405108
- Publication date Dec 30, 2021
- Tektronix, Inc.
- Sam J. Strickling
- G01 - MEASURING TESTING
Information Patent Application
TEST AND MEASUREMENT SYSTEM FOR ANALYZING DEVICES UNDER TEST
- Publication number 20210406144
- Publication date Dec 30, 2021
- Tektronix, Inc.
- Sam J. Strickling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATED RECOGNITION OF A DEVICE UNDER TEST
- Publication number 20210297882
- Publication date Sep 23, 2021
- Tektronix, Inc.
- Sam J. Strickling
- G01 - MEASURING TESTING
Information Patent Application
ADJUSTABLE RETIMER BUFFER
- Publication number 20210089421
- Publication date Mar 25, 2021
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSS-TALK GENERATION IN A MULTI-LANE LINK DURING LANE TESTING
- Publication number 20210081288
- Publication date Mar 18, 2021
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED PIN COUNT INTERFACE
- Publication number 20210056067
- Publication date Feb 25, 2021
- Intel Corporation
- Michelle Jen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-BAND MARGIN PROBING ON AN OPERATIONAL INTERCONNECT
- Publication number 20200364108
- Publication date Nov 19, 2020
- Intel Corporation
- Daniel S. Froelich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS AND DEVICES FOR HIGH-SPEED INPUT/OUTPUT MARGIN TES...
- Publication number 20200250368
- Publication date Aug 6, 2020
- Tektronix, Inc.
- Daniel S. Froelich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS AND DEVICES FOR HIGH-SPEED INPUT/OUTPUT MARGIN TES...
- Publication number 20200249275
- Publication date Aug 6, 2020
- Tektronix, Inc.
- Daniel S. Froelich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECT RETIMER ENHANCEMENTS
- Publication number 20200132760
- Publication date Apr 30, 2020
- Intel Corporation
- Daniel S. Froelich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED PIN COUNT INTERFACE
- Publication number 20190303338
- Publication date Oct 3, 2019
- Intel Corporation
- Michelle Jen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSS-TALK GENERATION IN A MULTI-LANE LINK DURING LANE TESTING
- Publication number 20190042380
- Publication date Feb 7, 2019
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, METHOD, AND APPARATUS FOR SRIS MODE SELECTION FOR PCIE
- Publication number 20190041898
- Publication date Feb 7, 2019
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADJUSTABLE RETIMER BUFFER
- Publication number 20180285227
- Publication date Oct 4, 2018
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-BAND MARGIN PROBING ON AN OPERATIONAL INTERCONNECT
- Publication number 20180267850
- Publication date Sep 20, 2018
- Intel Corporation
- Daniel S. Froelich
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
STANDARDIZED RETIMER
- Publication number 20170351640
- Publication date Dec 7, 2017
- Intel Corporation
- Manisha Nilange
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED PIN COUNT INTERFACE
- Publication number 20170344512
- Publication date Nov 30, 2017
- Intel Corporation
- Michelle Jen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SERIAL SIDEBAND SIGNALING LINK
- Publication number 20170235701
- Publication date Aug 17, 2017
- Intel Corporation
- Akshay Pethe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECT RETIMER ENHANCEMENTS
- Publication number 20160377679
- Publication date Dec 29, 2016
- Intel Corporation
- Daniel S. Froelich
- G01 - MEASURING TESTING
Information Patent Application
REDUCING PRECISION TIMING MEASUREMENT UNCERTAINTY
- Publication number 20160188524
- Publication date Jun 30, 2016
- Intel Corporation
- Daniel Froelich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA RATE DETECTION TO SIMPLIFY RETIMER LOGIC
- Publication number 20160182257
- Publication date Jun 23, 2016
- Intel Corporation
- Daniel Froelich
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PHYSICAL INTERFACE FOR A SERIAL INTERCONNECT
- Publication number 20160179710
- Publication date Jun 23, 2016
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST LOGIC FOR A SERIAL INTERCONNECT
- Publication number 20160179647
- Publication date Jun 23, 2016
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING

Daniel Froelich

Person

Patents Grantslast 30 patents

Test and measurement system for analyzing devices under test

System, method, and apparatus for SRIS mode selection for PCIE

Systems, methods and devices for high-speed input/output margin tes...

Margin test data tagging and predictive expected margins

Systems, methods, and devices for high-speed input/output margin te...

Cable condition indicator

Systems, methods and devices for high-speed input/output margin tes...

Systems, methods and devices for high-speed input/output margin tes...

Systems, methods, and devices for high-speed input/output margin te...

Test and measurement system for analyzing devices under test

Interconnect retimer enhancements

System, method, and apparatus for SRIS mode selection for PCIe

Cross-talk generation in a multi-lane link during lane testing

Adjustable retimer buffer

Reduced pin count interface

In-band margin probing on an operational interconnect

Adjustable retimer buffer

Cross-talk generation in a multi-lane link during lane testing

Reduced pin count interface

In-band margin probing on an operational interconnect

Interconnect retimer enhancements

Reduced pin count interface

Reducing precision timing measurement uncertainty

Physical interface for a serial interconnect

Method, apparatus and system for measuring latency in a physical un...

Test logic for a serial interconnect

Method, apparatus and system for measuring latency in a physical un...

Incorporating an independent logic block in a system-on-a-chip

Patents Applicationslast 30 patents

TEST AND MEASUREMENT SYSTEM FOR ANALYZING DEVICES UNDER TEST

SYSTEM, METHOD, AND APPARATUS FOR SRIS MODE SELECTION FOR PCIE

SYSTEMS, METHODS, AND DEVICES FOR HIGH-SPEED INPUT/OUTPUT MARGIN TE...

SYSTEMS, METHODS, AND DEVICES FOR HIGH-SPEED INPUT/OUTPUT MARGIN TE...

MARGIN TEST DATA TAGGING AND PREDICTIVE EXPECTED MARGINS

CABLE CONDITION INDICATOR

MULTIPLEXER-ENABLED CABLES AND TEST FIXTURES

SYSTEMS, METHODS AND DEVICES FOR HIGH-SPEED INPUT/OUTPUT MARGIN TES...

TEST AND MEASUREMENT SYSTEM FOR ANALYZING DEVICES UNDER TEST

AUTOMATED RECOGNITION OF A DEVICE UNDER TEST

ADJUSTABLE RETIMER BUFFER

CROSS-TALK GENERATION IN A MULTI-LANE LINK DURING LANE TESTING

REDUCED PIN COUNT INTERFACE

IN-BAND MARGIN PROBING ON AN OPERATIONAL INTERCONNECT

SYSTEMS, METHODS AND DEVICES FOR HIGH-SPEED INPUT/OUTPUT MARGIN TES...

SYSTEMS, METHODS AND DEVICES FOR HIGH-SPEED INPUT/OUTPUT MARGIN TES...

INTERCONNECT RETIMER ENHANCEMENTS

REDUCED PIN COUNT INTERFACE

CROSS-TALK GENERATION IN A MULTI-LANE LINK DURING LANE TESTING

SYSTEM, METHOD, AND APPARATUS FOR SRIS MODE SELECTION FOR PCIE

ADJUSTABLE RETIMER BUFFER

IN-BAND MARGIN PROBING ON AN OPERATIONAL INTERCONNECT

STANDARDIZED RETIMER

REDUCED PIN COUNT INTERFACE

SERIAL SIDEBAND SIGNALING LINK

INTERCONNECT RETIMER ENHANCEMENTS

REDUCING PRECISION TIMING MEASUREMENT UNCERTAINTY

DATA RATE DETECTION TO SIMPLIFY RETIMER LOGIC

PHYSICAL INTERFACE FOR A SERIAL INTERCONNECT

TEST LOGIC FOR A SERIAL INTERCONNECT