Daniel Gitlin

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for saving power in an integrated circuit
- Patent number 8,436,656
- Issue date May 7, 2013
- Tabula, Inc.
- Daniel Gitlin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit for protecting a transistor during the manufacture of an in...
- Patent number 7,956,385
- Issue date Jun 7, 2011
- Xilinx, Inc.
- Yuhao Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with backfilled isolation
- Patent number 7,936,006
- Issue date May 3, 2011
- Xilinx, Inc.
- Yuhao Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating CMOS-compatible non-volatile memory cell with...
- Patent number 7,839,693
- Issue date Nov 23, 2010
- Xilinix, Inc.
- Sunhom Paak
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of and circuit for protecting a transistor formed on a die
- Patent number 7,772,093
- Issue date Aug 10, 2010
- Xilinx, Inc.
- Yuhao Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-terminal non-volatile memory element with hybrid gate dielectric
- Patent number 7,687,797
- Issue date Mar 30, 2010
- Xilinx, Inc.
- James Karp
- G11 - INFORMATION STORAGE
Information Patent Grant
CMOS-compatible non-volatile memory cell with lateral inter-poly pr...
- Patent number 7,688,639
- Issue date Mar 30, 2010
- Xilinx, Inc.
- Sunhom Paak
- G11 - INFORMATION STORAGE
Information Patent Grant
CMOS-compatible non-volatile memory cell with lateral inter-poly pr...
- Patent number 7,294,888
- Issue date Nov 13, 2007
- Xilinx, Inc.
- Sunhom Paak
- G11 - INFORMATION STORAGE
Information Patent Grant
Layout correction algorithms for removing stress and other physical...
- Patent number 7,032,194
- Issue date Apr 18, 2006
- Xilinx, Inc.
- Shih-Cheng Hsueh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ballast resistor with reduced area for ESD protection
- Patent number 6,740,936
- Issue date May 25, 2004
- Xilinx, Inc.
- Daniel Gitlin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a zener diode
- Patent number 6,645,802
- Issue date Nov 11, 2003
- Xilinx, Inc.
- Sheau-Suey Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structures and methods for selectively applying a well bias to port...
- Patent number 6,621,325
- Issue date Sep 16, 2003
- Xilinx, Inc.
- Michael J. Hart
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile memory array using gate breakdown structures
- Patent number 6,549,458
- Issue date Apr 15, 2003
- Xilinx, Inc.
- Kameswara K. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory array using gate breakdown structures
- Patent number 6,522,582
- Issue date Feb 18, 2003
- Xilinx, Inc.
- Kameswara K. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Electrostatic-discharge protection circuit
- Patent number 6,268,639
- Issue date Jul 31, 2001
- Xilinx, Inc.
- Sheau-Suey Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three terminal non-volatile memory element
- Patent number 6,266,269
- Issue date Jul 24, 2001
- Xilinx, Inc.
- James Karp
- G11 - INFORMATION STORAGE
Information Patent Grant
Pass gate circuit with body bias control
- Patent number 5,880,620
- Issue date Mar 9, 1999
- Xilinx, Inc.
- Daniel Gitlin
- G11 - INFORMATION STORAGE
Information Patent Grant
Mixed mode RAM/ROM cell using antifuses
- Patent number 5,870,327
- Issue date Feb 9, 1999
- Xilinx, Inc.
- Daniel Gitlin
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR SAVING POWER IN AN INTEGRATED CIRCUIT
- Publication number 20110267103
- Publication date Nov 3, 2011
- Tabula, Inc.
- Daniel Gitlin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method of and circuit for protecting a transistor formed on a die
- Publication number 20090108337
- Publication date Apr 30, 2009
- Xilinx, Inc.
- Yuhao Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structures and methods for selectively applying a well bias to port...
- Publication number 20030053335
- Publication date Mar 20, 2003
- Xilinx, Inc.
- Michael J. Hart
- G06 - COMPUTING CALCULATING COUNTING

Daniel Gitlin

Person

Patents Grantslast 30 patents

Method and apparatus for saving power in an integrated circuit

Circuit for protecting a transistor during the manufacture of an in...

Semiconductor device with backfilled isolation

Method of fabricating CMOS-compatible non-volatile memory cell with...

Method of and circuit for protecting a transistor formed on a die

Three-terminal non-volatile memory element with hybrid gate dielectric

CMOS-compatible non-volatile memory cell with lateral inter-poly pr...

CMOS-compatible non-volatile memory cell with lateral inter-poly pr...

Layout correction algorithms for removing stress and other physical...

Ballast resistor with reduced area for ESD protection

Method of forming a zener diode

Structures and methods for selectively applying a well bias to port...

Non-volatile memory array using gate breakdown structures

Non-volatile memory array using gate breakdown structures

Electrostatic-discharge protection circuit

Three terminal non-volatile memory element

Pass gate circuit with body bias control

Mixed mode RAM/ROM cell using antifuses

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR SAVING POWER IN AN INTEGRATED CIRCUIT

Method of and circuit for protecting a transistor formed on a die

Structures and methods for selectively applying a well bias to port...