Daniel J. Pugh

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Fused memory and arithmetic circuit
- Patent number 12,034,446
- Issue date Jul 9, 2024
- Achronix Semiconductor Corporation
- Daniel Pugh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple mode arithmetic circuit
- Patent number 12,014,150
- Issue date Jun 18, 2024
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cascade communications between FPGA tiles
- Patent number 11,734,216
- Issue date Aug 22, 2023
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple mode arithmetic circuit
- Patent number 11,650,792
- Issue date May 16, 2023
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cascade communications between FPGA tiles
- Patent number 11,288,220
- Issue date Mar 29, 2022
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple mode arithmetic circuit
- Patent number 11,256,476
- Issue date Feb 22, 2022
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient FPGA multipliers
- Patent number 10,963,221
- Issue date Mar 30, 2021
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fused memory and arithmetic circuit
- Patent number 10,790,830
- Issue date Sep 29, 2020
- Achronix Semiconductor Corporation
- Daniel Pugh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Efficient FPGA multipliers
- Patent number 10,656,915
- Issue date May 19, 2020
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing mathematical and logical operations in multiple sub-cycles
- Patent number 8,463,836
- Issue date Jun 11, 2013
- Tabula, Inc.
- Daniel J. Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of providing a memory hierarchy
- Patent number 8,434,045
- Issue date Apr 30, 2013
- Tabula, Inc.
- Herman Schmit
- G11 - INFORMATION STORAGE
Information Patent Grant
IC that efficiently replicates a function to save logic and routing...
- Patent number 7,971,172
- Issue date Jun 28, 2011
- Tabula, Inc.
- Daniel J. Pugh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method of providing a memory hierarchy
- Patent number 7,930,666
- Issue date Apr 19, 2011
- Tabula, Inc.
- Herman Schmit
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for performing two's complement multiplication
- Patent number 7,818,361
- Issue date Oct 19, 2010
- Tabula, Inc.
- Daniel J. Pugh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Use of hybrid interconnect/logic circuits for multiplication
- Patent number 7,765,249
- Issue date Jul 27, 2010
- Tabula, Inc.
- Daniel J. Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of mapping memory blocks in a configurable integr...
- Patent number 7,587,697
- Issue date Sep 8, 2009
- Tabula, Inc.
- Herman Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid interconnect/logic circuits enabling efficient replication o...
- Patent number 7,372,297
- Issue date May 13, 2008
- Tabula Inc.
- Daniel J. Pugh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Gold code generator design
- Patent number 7,080,107
- Issue date Jul 18, 2006
- Intel Corporation
- Daniel J. Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Field programmable gate array core cell with efficient logic packing
- Patent number 7,009,421
- Issue date Mar 7, 2006
- Agate Logic, Inc.
- Daniel J. Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and implemention of a traceback-free parallel viterbi decoder
- Patent number 6,904,105
- Issue date Jun 7, 2005
- Intel Corporation
- Daniel J. Pugh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Gold code generator design
- Patent number 6,834,291
- Issue date Dec 21, 2004
- Intel Corporation
- Daniel J. Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Field programmable gate array core cell with efficient logic packing
- Patent number 6,801,052
- Issue date Oct 5, 2004
- Leopard Logic, Inc.
- Daniel J. Pugh
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Multiple Mode Arithmetic Circuit
- Publication number 20240248682
- Publication date Jul 25, 2024
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUSED MEMORY AND ARITHMETIC CIRCUIT
- Publication number 20240235556
- Publication date Jul 11, 2024
- Achronix Semiconductor Corporation
- Daniel Pugh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CASCADE COMMUNICATIONS BETWEEN FPGA TILES
- Publication number 20230325334
- Publication date Oct 12, 2023
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Mode Arithmetic Circuit
- Publication number 20230244446
- Publication date Aug 3, 2023
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CASCADE COMMUNICATIONS BETWEEN FPGA TILES
- Publication number 20220214990
- Publication date Jul 7, 2022
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Mode Arithmetic Circuit
- Publication number 20220129244
- Publication date Apr 28, 2022
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CASCADE COMMUNICATIONS BETWEEN FPGA TILES
- Publication number 20210117356
- Publication date Apr 22, 2021
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Mode Arithmetic Circuit
- Publication number 20210042087
- Publication date Feb 11, 2021
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUSED MEMORY AND ARITHMETIC CIRCUIT
- Publication number 20200373925
- Publication date Nov 26, 2020
- Achronix Semiconductor Corporation
- Daniel Pugh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
EFFICIENT FPGA MULTIPLIERS
- Publication number 20200195951
- Publication date Jun 18, 2020
- Achronix Semiconductor Corporation
- Daniel Pugh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
EFFICIENT FPGA MULTIPLIERS
- Publication number 20200019375
- Publication date Jan 16, 2020
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Gold code generator design
- Publication number 20050273480
- Publication date Dec 8, 2005
- Daniel J. Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Field programmable gate array core cell with efficient logic packing
- Publication number 20050040849
- Publication date Feb 24, 2005
- Leopard Logic, Inc.
- Daniel J. Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Field programmable gate array core cell with efficient logic packing
- Publication number 20030085733
- Publication date May 8, 2003
- Daniel J. Pugh
- G06 - COMPUTING CALCULATING COUNTING

Daniel J. Pugh

Person

Patents Grantslast 30 patents

Fused memory and arithmetic circuit

Multiple mode arithmetic circuit

Cascade communications between FPGA tiles

Multiple mode arithmetic circuit

Cascade communications between FPGA tiles

Multiple mode arithmetic circuit

Efficient FPGA multipliers

Fused memory and arithmetic circuit

Efficient FPGA multipliers

Performing mathematical and logical operations in multiple sub-cycles

System and method of providing a memory hierarchy

IC that efficiently replicates a function to save logic and routing...

System and method of providing a memory hierarchy

Method and apparatus for performing two's complement multiplication

Use of hybrid interconnect/logic circuits for multiplication

System and method of mapping memory blocks in a configurable integr...

Hybrid interconnect/logic circuits enabling efficient replication o...

Gold code generator design

Field programmable gate array core cell with efficient logic packing

Method and implemention of a traceback-free parallel viterbi decoder

Gold code generator design

Field programmable gate array core cell with efficient logic packing

Patents Applicationslast 30 patents

Multiple Mode Arithmetic Circuit

FUSED MEMORY AND ARITHMETIC CIRCUIT

CASCADE COMMUNICATIONS BETWEEN FPGA TILES

Multiple Mode Arithmetic Circuit

CASCADE COMMUNICATIONS BETWEEN FPGA TILES

Multiple Mode Arithmetic Circuit

CASCADE COMMUNICATIONS BETWEEN FPGA TILES

Multiple Mode Arithmetic Circuit

FUSED MEMORY AND ARITHMETIC CIRCUIT

EFFICIENT FPGA MULTIPLIERS

EFFICIENT FPGA MULTIPLIERS

Gold code generator design

Field programmable gate array core cell with efficient logic packing

Field programmable gate array core cell with efficient logic packing