Daniel Krueger

Person

Ft Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and systems to write to soft error upset tolerant latches
- Patent number 7,808,845
- Issue date Oct 5, 2010
- Intel Corporation
- Dan Krueger
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase-locked loop control circuit
- Patent number 7,317,778
- Issue date Jan 8, 2008
- Hewlett-Packard Development Company, L.P.
- Daniel Krueger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Triple redundant latch design with low delay time
- Patent number 7,215,581
- Issue date May 8, 2007
- Hewlett-Packard Development Company, L.P.
- Jonathan P Lotz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High reliability triple redundant latch with voting logic on each s...
- Patent number 7,179,690
- Issue date Feb 20, 2007
- Hewlett-Packard Development Company, L.P.
- Jonathan P Lotz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High reliability memory element with improved delay time
- Patent number 7,054,203
- Issue date May 30, 2006
- Hewlett-Packard Development Company, L.P.
- Jonathan P Lotz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High reliability triple redundant latch with voting logic on each s...
- Patent number 6,937,527
- Issue date Aug 30, 2005
- Hewlett-Packard Development Company, L.P.
- Jonathan P Lotz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Triple redundant latch design with storage node recovery
- Patent number 6,930,527
- Issue date Aug 16, 2005
- Hewlett-Packard Development Company, L.P.
- Manuel Cabanas-Holmen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Triple redundant latch design using a fail-over mechanism with backup
- Patent number 6,882,201
- Issue date Apr 19, 2005
- Hewlett-Packard Development Company, L.P.
- Kenneth Koch, II
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed incrementer/decrementer
- Patent number 6,665,698
- Issue date Dec 16, 2003
- Hewlett-Packard Development Company, L.P.
- Li C Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock distribution circuitry to different nodes on integrated circu...
- Patent number 6,594,772
- Issue date Jul 15, 2003
- Hewlett-Packard Development Company, L.P.
- Li C Tsai
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
POWER-FORWARDING BRIDGE FOR INTER-CHIP DATA SIGNAL TRANSFER
- Publication number 20220199537
- Publication date Jun 23, 2022
- Intel Corporation
- Zhiguo Qian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND SYSTEMS TO WRITE TO SOFT ERROR UPSET TOLERANT LATCHES
- Publication number 20100080072
- Publication date Apr 1, 2010
- Dan Krueger
- G11 - INFORMATION STORAGE
Information Patent Application
Memory element with improved soft-error rate
- Publication number 20060103442
- Publication date May 18, 2006
- Daniel W. Krueger
- G11 - INFORMATION STORAGE
Information Patent Application
High reliability triple redundant latch with voting logic on each s...
- Publication number 20050265089
- Publication date Dec 1, 2005
- Jonathan P. Lotz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Triple redundant latch design with low delay time
- Publication number 20050251729
- Publication date Nov 10, 2005
- Jonathan P. Lotz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
High reliability memory element with improved delay time
- Publication number 20050242828
- Publication date Nov 3, 2005
- Jonathan P. Lotz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TRIPLE REDUNDANT LATCH DESIGN WITH STORAGE NODE RECOVERY
- Publication number 20050168257
- Publication date Aug 4, 2005
- Manuel Cabanas-Holmen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and system for testing a logic design
- Publication number 20050144580
- Publication date Jun 30, 2005
- Daniel A. Berkram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Phase-locked loop control circuit
- Publication number 20040151271
- Publication date Aug 5, 2004
- Daniel Krueger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scan based multiple ring oscillator structure for on-chip speed mea...
- Publication number 20020129293
- Publication date Sep 12, 2002
- John F. Hutton
- G01 - MEASURING TESTING

Daniel Krueger

Person

Patents Grantslast 30 patents

Methods and systems to write to soft error upset tolerant latches

Phase-locked loop control circuit

Triple redundant latch design with low delay time

High reliability triple redundant latch with voting logic on each s...

High reliability memory element with improved delay time

High reliability triple redundant latch with voting logic on each s...

Triple redundant latch design with storage node recovery

Triple redundant latch design using a fail-over mechanism with backup

High speed incrementer/decrementer

Clock distribution circuitry to different nodes on integrated circu...

Patents Applicationslast 30 patents

POWER-FORWARDING BRIDGE FOR INTER-CHIP DATA SIGNAL TRANSFER

METHODS AND SYSTEMS TO WRITE TO SOFT ERROR UPSET TOLERANT LATCHES

Memory element with improved soft-error rate

High reliability triple redundant latch with voting logic on each s...

Triple redundant latch design with low delay time

High reliability memory element with improved delay time

TRIPLE REDUNDANT LATCH DESIGN WITH STORAGE NODE RECOVERY

Method and system for testing a logic design

Phase-locked loop control circuit

Scan based multiple ring oscillator structure for on-chip speed mea...