Daniel L. Ostapko

Person

Poughkeepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
System for using partitioned masks to build a chip
- Patent number 7,870,531
- Issue date Jan 11, 2011
- International Business Machines Corporation
- Subhrajit Bhattacharya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for using partitioned masks to build a chip
- Patent number 7,469,401
- Issue date Dec 23, 2008
- International Business Machines Corporation
- Subhrajit Bhattacharya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit logic with self compensating shapes
- Patent number 7,302,671
- Issue date Nov 27, 2007
- International Business Machines Corporation
- Fook-Luen Heng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lithographic process window optimization under complex constraints...
- Patent number 7,269,817
- Issue date Sep 11, 2007
- International Business Machines Corporation
- Fook-Luen Heng
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Integrated circuit logic with self compensating block delays
- Patent number 7,084,476
- Issue date Aug 1, 2006
- International Business Machines Corp.
- Puneet Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatus for performing slew dependent signal bounding...
- Patent number 6,430,731
- Issue date Aug 6, 2002
- International Business Machines Corporation
- Jin-Fuw Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partitioned mask layout
- Patent number 6,383,847
- Issue date May 7, 2002
- International Business Machines Corporation
- Gary S. Ditlow
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Clock distribution network with dual wire routing
- Patent number 6,144,224
- Issue date Nov 7, 2000
- International Business Machines Corporation
- Jin-Fuw Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock distribution network with dual wire routing
- Patent number 5,994,924
- Issue date Nov 30, 1999
- International Business Machines Corporation
- Jin-Fuw Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mapping and memory hardware for writing horizontal and vertical lines
- Patent number 4,559,611
- Issue date Dec 17, 1985
- International Business Machines Corporation
- Daniel L. Ostapko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Changeable decoder structure for a folded logic array
- Patent number 4,029,970
- Issue date Jun 14, 1977
- IBM Corporation
- Se J. Hong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Decoder structure for a folded logic array
- Patent number 4,025,799
- Issue date May 24, 1977
- IBM Corporation
- Dennis T. Cox
- G11 - INFORMATION STORAGE
Information Patent Grant
Logic array with testing circuitry
- Patent number 3,958,110
- Issue date May 18, 1976
- IBM Corporation
- Se J. Hong
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM FOR USING PARTITIONED MASKS TO BUILD A CHIP
- Publication number 20080216037
- Publication date Sep 4, 2008
- Subhrajit Bhattacharya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for using partitioned masks to build a chip
- Publication number 20070196958
- Publication date Aug 23, 2007
- International Business Machines Corporation
- Subhrajit Bhattacharya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit logic with self compensating block delays
- Publication number 20050189604
- Publication date Sep 1, 2005
- Puneet Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit logic with self compensating shapes
- Publication number 20050189605
- Publication date Sep 1, 2005
- Fook-Luen Heng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Lithographic process window optimization under complex constraints...
- Publication number 20050177810
- Publication date Aug 11, 2005
- International Business Machines Corporation
- Fook-Luen Heng
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Daniel L. Ostapko

Person

Patents Grantslast 30 patents

System for using partitioned masks to build a chip

Method for using partitioned masks to build a chip

Integrated circuit logic with self compensating shapes

Lithographic process window optimization under complex constraints...

Integrated circuit logic with self compensating block delays

Methods and apparatus for performing slew dependent signal bounding...

Partitioned mask layout

Clock distribution network with dual wire routing

Clock distribution network with dual wire routing

Mapping and memory hardware for writing horizontal and vertical lines

Changeable decoder structure for a folded logic array

Decoder structure for a folded logic array

Logic array with testing circuitry

Patents Applicationslast 30 patents

SYSTEM FOR USING PARTITIONED MASKS TO BUILD A CHIP

Method for using partitioned masks to build a chip

Integrated circuit logic with self compensating block delays

Integrated circuit logic with self compensating shapes

Lithographic process window optimization under complex constraints...