Daniel Mark NELSON

Person

Minneapolis, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Layout to minimize FET variation in small dimension photolithography
- Patent number 9,142,560
- Issue date Sep 22, 2015
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Layout to minimize FET variation in small dimension photolithography
- Patent number 8,860,141
- Issue date Oct 14, 2014
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Single cycle data copy for two-port SRAM
- Patent number 8,824,196
- Issue date Sep 2, 2014
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Data security for dynamic random access memory using body bias to c...
- Patent number 8,711,606
- Issue date Apr 29, 2014
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementing RC and coupling delay correction for SRAM
- Patent number 8,675,427
- Issue date Mar 18, 2014
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Data dependent SRAM write assist
- Patent number 8,520,429
- Issue date Aug 27, 2013
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Data security for dynamic random access memory using body bias to c...
- Patent number 8,467,230
- Issue date Jun 18, 2013
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Data security for dynamic random access memory at power-up
- Patent number 8,395,963
- Issue date Mar 12, 2013
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus to limit circuit delay dependence on voltage f...
- Patent number 8,344,782
- Issue date Jan 1, 2013
- International Business Machines Corporation
- Derick G. Behrends
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Single supply sub VDD bit-line precharge SRAM and method for level...
- Patent number 8,279,687
- Issue date Oct 2, 2012
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay chain burn-in for increased repeatability of physically unclo...
- Patent number 8,159,260
- Issue date Apr 17, 2012
- International Business Machines Corporation
- Derick Gardner Behrends
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Assessing resources required to complete a VLSI design
- Patent number 7,971,164
- Issue date Jun 28, 2011
- International Business Machines Corporation
- Derick G. Behrends
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing boosted wordline voltage in memories
- Patent number 7,924,633
- Issue date Apr 12, 2011
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementing enhanced SRAM stability and enhanced chip yield with c...
- Patent number 7,911,827
- Issue date Mar 22, 2011
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Design structure embodied in a machine readable medium for implemen...
- Patent number 7,788,554
- Issue date Aug 31, 2010
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus for implementing SRAM cell write performance evaluation
- Patent number 7,768,851
- Issue date Aug 3, 2010
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
High performance read bypass test for SRAM circuits
- Patent number 7,751,266
- Issue date Jul 6, 2010
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power level shifting latch circuits with gated feedback for hig...
- Patent number 7,737,757
- Issue date Jun 15, 2010
- International Business Machines Corporation
- Derick Gardner Behrends
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Implementing local evaluation of domino read SRAM with enhanced SRA...
- Patent number 7,724,586
- Issue date May 25, 2010
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementing local evaluation of domino read SRAM with enhanced SRA...
- Patent number 7,724,585
- Issue date May 25, 2010
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus to limit circuit delay dependence on voltage
- Patent number 7,714,630
- Issue date May 11, 2010
- International Business Machines Corporation
- Derick G. Behrends
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit for improved SRAM write around with reduced read access pen...
- Patent number 7,535,776
- Issue date May 19, 2009
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for implementing SRAM cell write performance evaluation
- Patent number 7,505,340
- Issue date Mar 17, 2009
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for multi-word write in domino read SRAMs
- Patent number 7,502,276
- Issue date Mar 10, 2009
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for reducing wiring and required number of redundant elements
- Patent number 7,443,744
- Issue date Oct 28, 2008
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR SELECTIVE WRITE ASSIST
- Publication number 20170117034
- Publication date Apr 27, 2017
- BROADCOM CORPORATION
- Travis R. HEBIG
- G11 - INFORMATION STORAGE
Information Patent Application
LOW POWER HIT BITLINE DRIVER FOR CONTENT-ADDRESSABLE MEMORY
- Publication number 20150262667
- Publication date Sep 17, 2015
- LSI Corporation
- TRAVIS HEBIG
- G11 - INFORMATION STORAGE
Information Patent Application
LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY
- Publication number 20140353764
- Publication date Dec 4, 2014
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Single Cycle Data Copy for Two-Port SRAM
- Publication number 20130258758
- Publication date Oct 3, 2013
- International Business Machines Corporation
- Derick G. Behrends
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING RC AND COUPLING DELAY CORRECTION FOR SRAM
- Publication number 20130235681
- Publication date Sep 12, 2013
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY
- Publication number 20130175631
- Publication date Jul 11, 2013
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO C...
- Publication number 20130148454
- Publication date Jun 13, 2013
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Data Dependent SRAM Write Assist
- Publication number 20120281457
- Publication date Nov 8, 2012
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY AT POWER-UP
- Publication number 20120147661
- Publication date Jun 14, 2012
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO C...
- Publication number 20120087176
- Publication date Apr 12, 2012
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
DELAY CHAIN BURN-IN FOR INCREASED REPEATABILITY OF PHYSICALLY UNCLO...
- Publication number 20120081143
- Publication date Apr 5, 2012
- International Business Machines Corporation
- Derick Gardner Behrends
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE SUPPLY SUB VDD BITLINE PRECHARGE SRAM AND METHOD FOR LEVEL S...
- Publication number 20110280088
- Publication date Nov 17, 2011
- International Business Machines Corporation
- CHAD A. ADAMS
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Apparatus to Limit Circuit Delay Dependence on Voltage f...
- Publication number 20110109366
- Publication date May 12, 2011
- International Business Machines Corporation
- Derick G. Behrends
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Implementing Boosted Wordline Voltage in Memories
- Publication number 20100214859
- Publication date Aug 26, 2010
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Implementing Enhanced SRAM Stability and Enhanced Chip Yield With C...
- Publication number 20100188886
- Publication date Jul 29, 2010
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Implementing Local Evaluation of Domino Read SRAM With Enhanced SRA...
- Publication number 20100046278
- Publication date Feb 25, 2010
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Implementing Local Evaluation of Domino Read SRAM With Enhanced SRA...
- Publication number 20100046277
- Publication date Feb 25, 2010
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Synchronization of Locations in Real and Virtual Worlds
- Publication number 20100030804
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Derick G. Behrends
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low Power Level Shifting Latch Circuits With Gated Feedback for Hig...
- Publication number 20100019824
- Publication date Jan 28, 2010
- International Business Machines Corporation
- Derick Gardner Behrends
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
High Performance Read Bypass Test for SRAM Circuits
- Publication number 20090323445
- Publication date Dec 31, 2009
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS TO LIMIT CIRCUIT DELAY DEPENDENCE ON VOLTAGE
- Publication number 20090309644
- Publication date Dec 17, 2009
- International Business Machines Corporation
- Derick G. Behrends
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Assessing Resources Required to Complete a VLSI Design
- Publication number 20090259977
- Publication date Oct 15, 2009
- Derick G. Behrends
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS FOR IMPLEMENTING SRAM CELL WRITE PERFORMANCE EVALUATION
- Publication number 20090116298
- Publication date May 7, 2009
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING SRAM CELL WRITE PERFORMANCE E...
- Publication number 20090059697
- Publication date Mar 5, 2009
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Apparatus for Implementing SRAM Cell Write Performance E...
- Publication number 20090063912
- Publication date Mar 5, 2009
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
ENHANCED SRAM REDUNDANCY CIRCUIT FOR REDUCING WIRING AND REQUIRED N...
- Publication number 20080273406
- Publication date Nov 6, 2008
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Enhanced SRAM Redundancy Circuit for Reducing Wiring and...
- Publication number 20080112219
- Publication date May 15, 2008
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Enhanced SRAM Redundancy Circuit for Reducing Wiring and...
- Publication number 20080112237
- Publication date May 15, 2008
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for implementing power saving for content addr...
- Publication number 20070047282
- Publication date Mar 1, 2007
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Computer program and method for simulating physical instruments
- Publication number 20030028361
- Publication date Feb 6, 2003
- Daniel W. Nelson
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS

Daniel Mark NELSON

Person

Patents Grantslast 30 patents

Layout to minimize FET variation in small dimension photolithography

Layout to minimize FET variation in small dimension photolithography

Single cycle data copy for two-port SRAM

Data security for dynamic random access memory using body bias to c...

Implementing RC and coupling delay correction for SRAM

Data dependent SRAM write assist

Data security for dynamic random access memory using body bias to c...

Data security for dynamic random access memory at power-up

Method and apparatus to limit circuit delay dependence on voltage f...

Single supply sub VDD bit-line precharge SRAM and method for level...

Delay chain burn-in for increased repeatability of physically unclo...

Assessing resources required to complete a VLSI design

Implementing boosted wordline voltage in memories

Implementing enhanced SRAM stability and enhanced chip yield with c...

Design structure embodied in a machine readable medium for implemen...

Apparatus for implementing SRAM cell write performance evaluation

High performance read bypass test for SRAM circuits

Low power level shifting latch circuits with gated feedback for hig...

Implementing local evaluation of domino read SRAM with enhanced SRA...

Implementing local evaluation of domino read SRAM with enhanced SRA...

Method and apparatus to limit circuit delay dependence on voltage

Circuit for improved SRAM write around with reduced read access pen...

Method for implementing SRAM cell write performance evaluation

Method and apparatus for multi-word write in domino read SRAMs

Method for reducing wiring and required number of redundant elements

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR SELECTIVE WRITE ASSIST

LOW POWER HIT BITLINE DRIVER FOR CONTENT-ADDRESSABLE MEMORY

LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY

Single Cycle Data Copy for Two-Port SRAM

IMPLEMENTING RC AND COUPLING DELAY CORRECTION FOR SRAM

LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY

DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO C...

Data Dependent SRAM Write Assist

DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY AT POWER-UP

DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO C...

DELAY CHAIN BURN-IN FOR INCREASED REPEATABILITY OF PHYSICALLY UNCLO...

SINGLE SUPPLY SUB VDD BITLINE PRECHARGE SRAM AND METHOD FOR LEVEL S...

Method and Apparatus to Limit Circuit Delay Dependence on Voltage f...

Implementing Boosted Wordline Voltage in Memories

Implementing Enhanced SRAM Stability and Enhanced Chip Yield With C...

Implementing Local Evaluation of Domino Read SRAM With Enhanced SRA...

Implementing Local Evaluation of Domino Read SRAM With Enhanced SRA...

Synchronization of Locations in Real and Virtual Worlds

Low Power Level Shifting Latch Circuits With Gated Feedback for Hig...

High Performance Read Bypass Test for SRAM Circuits

METHOD AND APPARATUS TO LIMIT CIRCUIT DELAY DEPENDENCE ON VOLTAGE

Assessing Resources Required to Complete a VLSI Design

APPARATUS FOR IMPLEMENTING SRAM CELL WRITE PERFORMANCE EVALUATION

METHOD AND APPARATUS FOR IMPLEMENTING SRAM CELL WRITE PERFORMANCE E...

Method and Apparatus for Implementing SRAM Cell Write Performance E...

ENHANCED SRAM REDUNDANCY CIRCUIT FOR REDUCING WIRING AND REQUIRED N...

Method and Enhanced SRAM Redundancy Circuit for Reducing Wiring and...

Method and Enhanced SRAM Redundancy Circuit for Reducing Wiring and...

Method and apparatus for implementing power saving for content addr...

Computer program and method for simulating physical instruments