Daniel P. Shimizu

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Hillsborough, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Subframe level latency de-interlacing method and apparatus
- Patent number 9,277,168
- Issue date Mar 1, 2016
- Advanced Micro Devices, Inc.
- Rex George
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic leakage control using selective back-biasing
- Patent number 8,314,647
- Issue date Nov 20, 2012
- Advanced Micro Devices, Inc.
- Daniel Shimizu
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
SUBFRAME LEVEL LATENCY DE-INTERLACING METHOD AND APPARATUS
- Publication number 20140002733
- Publication date Jan 2, 2014
- Advanced Micro Devices, Inc.
- Rex George
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DYNAMIC LEAKAGE CONTROL USING SELECTIVE BACK-BIASING
- Publication number 20110279938
- Publication date Nov 17, 2011
- Advanced Micro Devices, Inc.
- Daniel Shimizu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dynamic leakage control using selective back-biasing
- Publication number 20080197914
- Publication date Aug 21, 2008
- Daniel Shimizu
- H03 - BASIC ELECTRONIC CIRCUITRY