Daniel W. Fisher

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Clifton Park, NY, US

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Patents Grantslast 30 patents

Information Patent Grant
Methods and structures for mitigating ESD during wafer bonding
- Patent number 10,236,263
- Issue date Mar 19, 2019
- GLOBALFOUNDRIES Inc.
- Luke England
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned lithographic patterning with variable spacings
- Patent number 9,711,447
- Issue date Jul 18, 2017
- GLOBALFOUNDRIES Inc.
- Jiehui Shu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND STRUCTURES FOR MITIGATING ESD DURING WAFER BONDING
- Publication number 20190067217
- Publication date Feb 28, 2019
- GLOBALFOUNDRIES INC.
- Luke England
- H01 - BASIC ELECTRIC ELEMENTS