Daniel Y. Cheung

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Cupertino, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Method and circuitry for phase align detection in multi-clock domain
- Patent number 6,900,674
- Issue date May 31, 2005
- Sun Microsystems, Inc.
- Massimo Sutera
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Glitch free programmable delay line for edge sensitive design
- Publication number 20040225976
- Publication date Nov 11, 2004
- Daniel Y. Cheung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and circuitry for phase align detection in multi-clock domain
- Publication number 20040100308
- Publication date May 27, 2004
- Sun Microsystems, Inc.
- Massimo Sutera
- H03 - BASIC ELECTRONIC CIRCUITRY