Darrell D. BOGGS

Person

Aloha, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory type which is cacheable yet inaccessible by speculative inst...
- Patent number 10,642,744
- Issue date May 5, 2020
- NVIDIA Corporation
- Darrell D. Boggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lazy runahead operation for a microprocessor
- Patent number 9,891,972
- Issue date Feb 13, 2018
- NVIDIA Corporation
- Magnus Ekman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Checkpointed buffer for re-entry from runahead
- Patent number 9,875,105
- Issue date Jan 23, 2018
- NVIDIA Corporation
- Guillermo J. Rozas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Queued instruction re-dispatch after runahead
- Patent number 9,823,931
- Issue date Nov 21, 2017
- NVIDIA Corporation
- Guillermo J. Rozas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing potentially invalid results during runahead
- Patent number 9,740,553
- Issue date Aug 22, 2017
- NVIDIA Corporation
- Bruce Holmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lazy runahead operation for a microprocessor
- Patent number 9,632,976
- Issue date Apr 25, 2017
- NVIDIA Corporation
- Guillermo J. Rozas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic configuration of processing pipeline based on determined ty...
- Patent number 9,563,432
- Issue date Feb 7, 2017
- NVIDIA Corporation
- Ross Segelken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for assigning thread priority in a processor o...
- Patent number 8,850,165
- Issue date Sep 30, 2014
- Intel Corporation
- David W. Burns
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for assigning thread priority in a processor o...
- Patent number 7,987,346
- Issue date Jul 26, 2011
- Intel Corporation
- David Burns
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for assigning thread priority in a processor o...
- Patent number 7,877,583
- Issue date Jan 25, 2011
- Intel Corporation
- David W. Burns
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable event driven yield mechanism which may activate servic...
- Patent number 7,849,465
- Issue date Dec 7, 2010
- Intel Corporation
- Xiang Zou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for assigning thread priority in a processor o...
- Patent number 7,454,600
- Issue date Nov 18, 2008
- Intel Corporation
- David W. Burns
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Alteration of functional unit partitioning scheme in multithreaded...
- Patent number 7,366,879
- Issue date Apr 29, 2008
- Intel Corporation
- Dion Rodgers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for processing an event occurrence within a mu...
- Patent number 7,353,370
- Issue date Apr 1, 2008
- Intel Corporation
- Dion Rodgers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-threading techniques for a processor utilizing a replay queue
- Patent number 7,219,349
- Issue date May 15, 2007
- Intel Corporation
- Amit A. Merchant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor with customer code store
- Patent number 7,216,220
- Issue date May 8, 2007
- Stexar Corp.
- Gary L Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor with a replay system that includes a replay queue for imp...
- Patent number 7,200,737
- Issue date Apr 3, 2007
- Intel Corporation
- Amit A. Merchant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prediction of load-store dependencies in a processing agent
- Patent number 7,181,598
- Issue date Feb 20, 2007
- Intel Corporation
- Stephan J. Jourdan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface to a memory system for a processor having a replay system
- Patent number 7,089,409
- Issue date Aug 8, 2006
- Intel Corporation
- Amit A. Merchant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for managing resources in a multithreaded proc...
- Patent number 7,051,329
- Issue date May 23, 2006
- Intel Corporation
- Darrell D. Boggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for processing an event occurrence for a least...
- Patent number 7,039,794
- Issue date May 2, 2006
- Intel Corporation
- Dion Rodgers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determining whether thread fetch operation will be blocked due to p...
- Patent number 7,010,669
- Issue date Mar 7, 2006
- Intel Corporation
- David W. Burns
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Breaking replay dependency loops in a processor using a rescheduled...
- Patent number 6,981,129
- Issue date Dec 27, 2005
- Intel Corporation
- Darrell D. Boggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for entering and exiting multiple threads with...
- Patent number 6,889,319
- Issue date May 3, 2005
- Intel Corporation
- Dion Rodgers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for rescheduling multiple micro-operations in...
- Patent number 6,877,086
- Issue date Apr 5, 2005
- Intel Corporation
- Darrell D. Boggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Branch ordering buffer
- Patent number 6,799,268
- Issue date Sep 28, 2004
- Intel Corporation
- Darrell D. Boggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control word register renaming
- Patent number 6,779,103
- Issue date Aug 17, 2004
- Intel Corporation
- William Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having replay architecture with fast and slow replay paths
- Patent number 6,735,688
- Issue date May 11, 2004
- Intel Corporation
- Michael D. Upton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface to a memory system for a processor having a replay system
- Patent number 6,665,792
- Issue date Dec 16, 2003
- Intel Corporation
- Amit A. Merchant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determination of approaching instruction starvation of threads base...
- Patent number 6,651,158
- Issue date Nov 18, 2003
- Intel Corporation
- David W. Burns
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY TYPE WHICH IS CACHEABLE YET INACCESSIBLE BY SPECULATIVE INST...
- Publication number 20190004961
- Publication date Jan 3, 2019
- NVIDIA Corporation
- Darrell D. BOGGS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAZY RUNAHEAD OPERATION FOR A MICROPROCESSOR
- Publication number 20170199778
- Publication date Jul 13, 2017
- Magnus Ekman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CONFIGURATION OF PROCESSING PIPELINE BASED ON DETERMINED TY...
- Publication number 20140317382
- Publication date Oct 23, 2014
- NVIDIA Corporation
- Ross Segelken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUEUED INSTRUCTION RE-DISPATCH AFTER RUNAHEAD
- Publication number 20140189313
- Publication date Jul 3, 2014
- NVIDIA Corporation
- Guillermo J. Rozas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION CATEGORIZATION FOR RUNAHEAD OPERATION
- Publication number 20140164738
- Publication date Jun 12, 2014
- NVIDIA Corporation
- Magnus Ekman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAZY RUNAHEAD OPERATION FOR A MICROPROCESSOR
- Publication number 20140164736
- Publication date Jun 12, 2014
- NVIDIA Corporation
- Guillermo J. Rozas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING POTENTIALLY INVALID RESULTS DURING RUNAHEAD
- Publication number 20140136891
- Publication date May 15, 2014
- NVIDIA CORPORATION
- Bruce Holmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHECKPOINTED BUFFER FOR RE-ENTRY FROM RUNAHEAD
- Publication number 20130297911
- Publication date Nov 7, 2013
- NVIDIA Corporation
- Guillermo J. Rozas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Assigning Thread Priority in a Processor o...
- Publication number 20110239221
- Publication date Sep 29, 2011
- David W. Burns
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ASSIGNING THREAD PRIORITY IN A PROCESSOR O...
- Publication number 20110113222
- Publication date May 12, 2011
- Intel Corporation
- David W. BURNS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ASSIGNING THREAD PRIORITY IN A PROCESSOR O...
- Publication number 20090070562
- Publication date Mar 12, 2009
- Intel Corporation
- David W. BURNS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bit field selection instruction
- Publication number 20070124631
- Publication date May 31, 2007
- Darrell D. Boggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction packer for digital signal processor
- Publication number 20070083736
- Publication date Apr 12, 2007
- Aravindh Baktha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable event driven yield mechanism which may activate servic...
- Publication number 20060294347
- Publication date Dec 28, 2006
- Xiang Zou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Add-shift-round instruction with dual-use source operand for DSP
- Publication number 20060218380
- Publication date Sep 28, 2006
- Stexar Corporation
- Darrell D. Boggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction with dual-use source providing both an operand value an...
- Publication number 20060218377
- Publication date Sep 28, 2006
- Stexar Corporation
- Darrell D. Boggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Rounding correction for add-shift-round instruction with dual-use s...
- Publication number 20060218381
- Publication date Sep 28, 2006
- Stexar Corporation
- Chad E. Fogg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clip-and-pack instruction for processor
- Publication number 20060095713
- Publication date May 4, 2006
- Stexar Corporation
- Darrell D. Boggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clip instruction for processor
- Publication number 20060095714
- Publication date May 4, 2006
- Stexar Corporation
- Darrell D. Boggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable matrix register file
- Publication number 20060036801
- Publication date Feb 16, 2006
- Christpher S. Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Microprocessor with branch target determination in decoded microins...
- Publication number 20060015708
- Publication date Jan 19, 2006
- Darrell D. Boggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Microprocessor with customer code store
- Publication number 20060015707
- Publication date Jan 19, 2006
- Gary L. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for processing an event occurrence within a mu...
- Publication number 20050132376
- Publication date Jun 16, 2005
- Dion Rodgers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for entering and exiting multiple threads with...
- Publication number 20050038980
- Publication date Feb 17, 2005
- Dion Rodgers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor having a RAT state history recovery mechanism
- Publication number 20040177239
- Publication date Sep 9, 2004
- David W. Clift
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interface to a memory system for a processor having a replay system
- Publication number 20040083351
- Publication date Apr 29, 2004
- Amit A. Merchant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for resolving instruction starvation in a proc...
- Publication number 20040078794
- Publication date Apr 22, 2004
- David W. Burns
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Prediction of load-store dependencies in a processing agent
- Publication number 20030217251
- Publication date Nov 20, 2003
- Stephan J. Jourdan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for processing an event occurrence for at leas...
- Publication number 20030061258
- Publication date Mar 27, 2003
- Dion Rodgers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for an INUSE field resource management scheme
- Publication number 20030023816
- Publication date Jan 30, 2003
- Alan B. Kyker
- G06 - COMPUTING CALCULATING COUNTING

Darrell D. BOGGS

Person

Patents Grantslast 30 patents

Memory type which is cacheable yet inaccessible by speculative inst...

Lazy runahead operation for a microprocessor

Checkpointed buffer for re-entry from runahead

Queued instruction re-dispatch after runahead

Managing potentially invalid results during runahead

Lazy runahead operation for a microprocessor

Dynamic configuration of processing pipeline based on determined ty...

Method and apparatus for assigning thread priority in a processor o...

Method and apparatus for assigning thread priority in a processor o...

Method and apparatus for assigning thread priority in a processor o...

Programmable event driven yield mechanism which may activate servic...

Method and apparatus for assigning thread priority in a processor o...

Alteration of functional unit partitioning scheme in multithreaded...

Method and apparatus for processing an event occurrence within a mu...

Multi-threading techniques for a processor utilizing a replay queue

Microprocessor with customer code store

Processor with a replay system that includes a replay queue for imp...

Prediction of load-store dependencies in a processing agent

Interface to a memory system for a processor having a replay system

Method and apparatus for managing resources in a multithreaded proc...

Method and apparatus for processing an event occurrence for a least...

Determining whether thread fetch operation will be blocked due to p...

Breaking replay dependency loops in a processor using a rescheduled...

Method and apparatus for entering and exiting multiple threads with...

Method and apparatus for rescheduling multiple micro-operations in...

Branch ordering buffer

Control word register renaming

Processor having replay architecture with fast and slow replay paths

Interface to a memory system for a processor having a replay system

Determination of approaching instruction starvation of threads base...

Patents Applicationslast 30 patents

MEMORY TYPE WHICH IS CACHEABLE YET INACCESSIBLE BY SPECULATIVE INST...

LAZY RUNAHEAD OPERATION FOR A MICROPROCESSOR

DYNAMIC CONFIGURATION OF PROCESSING PIPELINE BASED ON DETERMINED TY...

QUEUED INSTRUCTION RE-DISPATCH AFTER RUNAHEAD

INSTRUCTION CATEGORIZATION FOR RUNAHEAD OPERATION

LAZY RUNAHEAD OPERATION FOR A MICROPROCESSOR

MANAGING POTENTIALLY INVALID RESULTS DURING RUNAHEAD

CHECKPOINTED BUFFER FOR RE-ENTRY FROM RUNAHEAD

Method and Apparatus for Assigning Thread Priority in a Processor o...

METHOD AND APPARATUS FOR ASSIGNING THREAD PRIORITY IN A PROCESSOR O...

METHOD AND APPARATUS FOR ASSIGNING THREAD PRIORITY IN A PROCESSOR O...

Bit field selection instruction

Instruction packer for digital signal processor

Programmable event driven yield mechanism which may activate servic...

Add-shift-round instruction with dual-use source operand for DSP

Instruction with dual-use source providing both an operand value an...

Rounding correction for add-shift-round instruction with dual-use s...

Clip-and-pack instruction for processor

Clip instruction for processor

Scalable matrix register file

Microprocessor with branch target determination in decoded microins...

Microprocessor with customer code store

Method and apparatus for processing an event occurrence within a mu...

Method and apparatus for entering and exiting multiple threads with...

Processor having a RAT state history recovery mechanism

Interface to a memory system for a processor having a replay system

Method and apparatus for resolving instruction starvation in a proc...

Prediction of load-store dependencies in a processing agent

Method and apparatus for processing an event occurrence for at leas...

Method and system for an INUSE field resource management scheme