Darrell S. McGinnis

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Cornelius, OR, US

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Patents Grantslast 30 patents

Information Patent Grant
Mechanisms and techniques for providing cache tags in dynamic rando...
- Patent number 8,612,832
- Issue date Dec 17, 2013
- Intel Corporation
- Darrell S. McGinnis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for scalable clock gearing mechanism
- Patent number 7,249,274
- Issue date Jul 24, 2007
- Intel Corporation
- Darrell S. McGinnis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retry of a device read transaction
- Patent number 7,177,989
- Issue date Feb 13, 2007
- Intel Corporation
- Darrell S. McGinnis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logical to physical address mapping of chip selects
- Patent number 7,133,960
- Issue date Nov 7, 2006
- Intel Corporation
- Derek A Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for dynamic rank specific timing adjustments for...
- Patent number 7,127,584
- Issue date Oct 24, 2006
- Intel Corporation
- Derek A. Thompson
- G11 - INFORMATION STORAGE
Information Patent Grant
Write pointer error recovery systems and methods
- Patent number 7,106,633
- Issue date Sep 12, 2006
- Intel Corporation
- Derek A Thompson
- G11 - INFORMATION STORAGE
Information Patent Grant
Write pointer error recovery
- Patent number 6,956,775
- Issue date Oct 18, 2005
- Intel Corporation
- Derek A. Thompson
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
HYBRID MEMORY ARCHITECTURE
- Publication number 20160224252
- Publication date Aug 4, 2016
- Intel Corporation
- Steven R. Hutsell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISMS AND TECHNIQUES FOR PROVIDING CACHE TAGS IN DYNAMIC RANDO...
- Publication number 20120254700
- Publication date Oct 4, 2012
- Darrell S. McGinnis
- G06 - COMPUTING CALCULATING COUNTING