Darren Kerr

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Programmable arrayed processing engine architecture for a network s...
- Patent number 7,895,412
- Issue date Feb 22, 2011
- Cisco Tehnology, Inc.
- Darren Kerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for a processor complex of an arrayed pipelined proces...
- Patent number 7,380,101
- Issue date May 27, 2008
- Cisco Technology, Inc.
- Michael L. Wright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible, high performance support for QoS on an arbitrary number o...
- Patent number 7,292,578
- Issue date Nov 6, 2007
- Cisco Technology, Inc.
- Darren Kerr
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Zero overhead resource locks with attributes
- Patent number 7,290,105
- Issue date Oct 30, 2007
- Cisco Technology, Inc.
- Robert E. Jeter, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selected register decode values for pipeline stage register addressing
- Patent number 7,139,899
- Issue date Nov 21, 2006
- Cisco Technology, Inc.
- Darren Kerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Barrier synchronization mechanism for processors of a systolic array
- Patent number 7,100,021
- Issue date Aug 29, 2006
- Cisco Technology, Inc.
- John William Marshall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Boundary synchronization mechanism for a processor of a systolic array
- Patent number 6,986,022
- Issue date Jan 10, 2006
- Cisco Technology, Inc.
- John William Marshall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packet striping across a parallel header processor
- Patent number 6,965,615
- Issue date Nov 15, 2005
- Cisco Technology, Inc.
- Darren Kerr
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Tightly coupled software protocol decode with hardware data encryption
- Patent number 6,920,562
- Issue date Jul 19, 2005
- Cisco Technology, Inc.
- Darren Kerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for a processor complex of an arrayed pipelined proces...
- Patent number 6,836,838
- Issue date Dec 28, 2004
- Cisco Technology, Inc.
- Michael L. Wright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequence control mechanism for enabling out of order context proces...
- Patent number 6,804,815
- Issue date Oct 12, 2004
- Cisco Technology, Inc.
- Darren Kerr
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable processing engine for efficiently processing transient...
- Patent number 6,513,108
- Issue date Jan 28, 2003
- Cisco Technology, Inc.
- Darren Kerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for a process complex of an arrayed pipelined processi...
- Patent number 6,442,669
- Issue date Aug 27, 2002
- Cisco Technology, Inc.
- Michael L. Wright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronization and control system for an arrayed processing engine
- Patent number 6,272,621
- Issue date Aug 7, 2001
- Cisco Technology, Inc.
- Kenneth Michael Key
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for passing data among processor complex stage...
- Patent number 6,195,739
- Issue date Feb 27, 2001
- Cisco Technology, Inc.
- Michael L. Wright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel processor with debug capability
- Patent number 6,173,386
- Issue date Jan 9, 2001
- Cisco Technology, Inc.
- Kenneth Michael Key
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronization and control system for an arrayed processing engine
- Patent number 6,119,215
- Issue date Sep 12, 2000
- Cisco Technology, Inc.
- Kenneth Michael Key
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for context switching between processing elements in a pipel...
- Patent number 6,101,599
- Issue date Aug 8, 2000
- Cisco Technology, Inc.
- Michael L. Wright
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Architecture for a processor complex of an arrayed pipelined proces...
- Publication number 20050125643
- Publication date Jun 9, 2005
- Michael L. Wright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTED REGISTER DECODE VALUES FOR PIPELINE STAGE REGISTER ADDRESSING
- Publication number 20030159021
- Publication date Aug 21, 2003
- DARREN KERR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Architecture for a processor complex of an arrayed pipelined proces...
- Publication number 20010000046
- Publication date Mar 15, 2001
- Michael L. Wright
- G06 - COMPUTING CALCULATING COUNTING

Darren Kerr

Person

Patents Grantslast 30 patents

Programmable arrayed processing engine architecture for a network s...

Architecture for a processor complex of an arrayed pipelined proces...

Flexible, high performance support for QoS on an arbitrary number o...

Zero overhead resource locks with attributes

Selected register decode values for pipeline stage register addressing

Barrier synchronization mechanism for processors of a systolic array

Boundary synchronization mechanism for a processor of a systolic array

Packet striping across a parallel header processor

Tightly coupled software protocol decode with hardware data encryption

Architecture for a processor complex of an arrayed pipelined proces...

Sequence control mechanism for enabling out of order context proces...

Programmable processing engine for efficiently processing transient...

Architecture for a process complex of an arrayed pipelined processi...

Synchronization and control system for an arrayed processing engine

Method and apparatus for passing data among processor complex stage...

Parallel processor with debug capability

Synchronization and control system for an arrayed processing engine

System for context switching between processing elements in a pipel...

Patents Applicationslast 30 patents

Architecture for a processor complex of an arrayed pipelined proces...

SELECTED REGISTER DECODE VALUES FOR PIPELINE STAGE REGISTER ADDRESSING

Architecture for a processor complex of an arrayed pipelined proces...