Dave Bach

Person

Shewabury, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Layered super-reticle computing : architectures and methods
- Patent number 11,656,662
- Issue date May 23, 2023
- Intel Corporation
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layered super-reticle computing : architectures and methods
- Patent number 10,963,022
- Issue date Mar 30, 2021
- Intel Corporation
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layered super-reticle computing: architectures and methods
- Patent number 10,691,182
- Issue date Jun 23, 2020
- Intel Corporation
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ceramic package substrate with recessed device
- Patent number 8,264,846
- Issue date Sep 11, 2012
- Intel Corporation
- Christopher C. Jones
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Individual sub-assembly containing a ceramic interposer, silicon vo...
- Patent number 7,675,160
- Issue date Mar 9, 2010
- Intel Corporation
- Sriram Dattaguru
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Dual interposer packaging for high density interconnect
- Patent number 6,812,485
- Issue date Nov 2, 2004
- Hewlett-Packard Development Company, L.P.
- Sharad M. Shah
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS
- Publication number 20210255674
- Publication date Aug 19, 2021
- Intel Corporation
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS
- Publication number 20200371566
- Publication date Nov 26, 2020
- Intel Corporation
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS
- Publication number 20190354146
- Publication date Nov 21, 2019
- Intel Corporation
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Individual sub-assembly containing a ceramic interposer, silicon vo...
- Publication number 20080157274
- Publication date Jul 3, 2008
- Sriram Dattaguru
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Ceramic interposer with silicon voltage regulator and array capacit...
- Publication number 20080157343
- Publication date Jul 3, 2008
- Sriram Dattaguru
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
CERAMIC PACKAGE SUBSTRATE WITH RECESSED DEVICE
- Publication number 20080142961
- Publication date Jun 19, 2008
- Christopher C. Jones
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Dual interposer packaging for high density interconnect
- Publication number 20030123231
- Publication date Jul 3, 2003
- Sharad M. Shah
- G01 - MEASURING TESTING

Person

Patents Grantslast 30 patents

Layered super-reticle computing : architectures and methods

Layered super-reticle computing : architectures and methods

Layered super-reticle computing: architectures and methods

Ceramic package substrate with recessed device

Individual sub-assembly containing a ceramic interposer, silicon vo...

Dual interposer packaging for high density interconnect

Patents Applicationslast 30 patents

LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS

LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS

LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS

Individual sub-assembly containing a ceramic interposer, silicon vo...

Ceramic interposer with silicon voltage regulator and array capacit...

CERAMIC PACKAGE SUBSTRATE WITH RECESSED DEVICE

Dual interposer packaging for high density interconnect