David A. Abercrombie

Person

Gresham, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Yield profile manipulator
- Patent number 7,930,655
- Issue date Apr 19, 2011
- LSI Corporation
- ChandraSekhar Desu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for calculating high-resolution wafer parameter profiles
- Patent number 7,653,523
- Issue date Jan 26, 2010
- LSI Corporation
- Bruce Whitefield
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus for wafer patterning to reduce edge exclusion zone
- Patent number 7,460,211
- Issue date Dec 2, 2008
- LSI Corporation
- Bruce Whitefield
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of isolating sources of variance in parametric data
- Patent number 7,454,387
- Issue date Nov 18, 2008
- LSI Corporation
- David Abercrombie
- G05 - CONTROLLING REGULATING
Information Patent Grant
Yield profile manipulator
- Patent number 7,395,522
- Issue date Jul 1, 2008
- LSI Corporation
- ChandraSekhar Desu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to selectively identify reliability risk die based on charac...
- Patent number 7,390,680
- Issue date Jun 24, 2008
- LSI Corporation
- Ramon Gonzales
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for analyzing manufacturing data
- Patent number 7,174,281
- Issue date Feb 6, 2007
- LSI Logic Corporation
- David Abercrombie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pattern component analysis and manipulation
- Patent number 7,137,098
- Issue date Nov 14, 2006
- LSI Logic Corporation
- Bruce J. Whitefield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parametric outlier detection
- Patent number 7,062,415
- Issue date Jun 13, 2006
- LSI Logic Corporation
- Bruce J. Whitefield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Substrate profile analysis
- Patent number 7,039,556
- Issue date May 2, 2006
- LSI Logic Corporation
- Bruce J. Whitefield
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Optimization of die yield in a silicon wafer “sweet spot”
- Patent number 6,980,917
- Issue date Dec 27, 2005
- LSI Logic Corporation
- Mark Ward
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method to selectively identify reliability risk die based on charac...
- Patent number 6,880,140
- Issue date Apr 12, 2005
- LSI Logic Corporation
- Ramon Gonzales
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Adaptive off tester screening method based on intrinsic die paramet...
- Patent number 6,807,655
- Issue date Oct 19, 2004
- LSI Logic Corporation
- Manu Rehani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Heaviest only fail potential
- Patent number 6,658,361
- Issue date Dec 2, 2003
- LSI Logic Corporation
- Manu Rehani
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Yield Profile Manipulator
- Publication number 20080216048
- Publication date Sep 4, 2008
- LSI Corporation
- ChandraSekhar Desu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS FOR WAFER PATTERNING TO REDUCE EDGE EXCLUSION ZONE
- Publication number 20060191634
- Publication date Aug 31, 2006
- Bruce Whitefield
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHOD OF WAFER PATTERNING FOR REDUCING EDGE EXCLUSION ZONE
- Publication number 20060094246
- Publication date May 4, 2006
- LSI Logic Corporation
- Bruce Whitefield
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Pattern component analysis and manipulation
- Publication number 20060059452
- Publication date Mar 16, 2006
- Bruce J. Whitefield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Substrate profile analysis
- Publication number 20050288896
- Publication date Dec 29, 2005
- Bruce J. Whitefield
- G05 - CONTROLLING REGULATING
Information Patent Application
Yield profile manipulator
- Publication number 20050229144
- Publication date Oct 13, 2005
- Chandra Sekhar Desu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method to selectively identify reliability risk die based on charac...
- Publication number 20050145841
- Publication date Jul 7, 2005
- LSI Logic Corporation
- Ramon Gonzales
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for calculating high-resolution wafer parameter profiles
- Publication number 20050132308
- Publication date Jun 16, 2005
- Bruce Whitefield
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of isolating sources of variance in parametric data
- Publication number 20050060336
- Publication date Mar 17, 2005
- David Abercrombie
- G05 - CONTROLLING REGULATING
Information Patent Application
Method to selectively identify reliability risk die based on charac...
- Publication number 20040249598
- Publication date Dec 9, 2004
- Ramon Gonzales
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Optimization of die yield in a silicon wafer "sweet spot"
- Publication number 20040128630
- Publication date Jul 1, 2004
- Mark Ward
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method for analyzing manufacturing data
- Publication number 20030208286
- Publication date Nov 6, 2003
- LSI Logic Corporation
- David Abercrombie
- G06 - COMPUTING CALCULATING COUNTING

David A. Abercrombie

Person

Patents Grantslast 30 patents

Yield profile manipulator

Method for calculating high-resolution wafer parameter profiles

Apparatus for wafer patterning to reduce edge exclusion zone

Method of isolating sources of variance in parametric data

Yield profile manipulator

Method to selectively identify reliability risk die based on charac...

Method for analyzing manufacturing data

Pattern component analysis and manipulation

Parametric outlier detection

Substrate profile analysis

Optimization of die yield in a silicon wafer “sweet spot”

Method to selectively identify reliability risk die based on charac...

Adaptive off tester screening method based on intrinsic die paramet...

Heaviest only fail potential

Patents Applicationslast 30 patents

Yield Profile Manipulator

APPARATUS FOR WAFER PATTERNING TO REDUCE EDGE EXCLUSION ZONE

METHOD OF WAFER PATTERNING FOR REDUCING EDGE EXCLUSION ZONE

Pattern component analysis and manipulation

Substrate profile analysis

Yield profile manipulator

Method to selectively identify reliability risk die based on charac...

Method for calculating high-resolution wafer parameter profiles

Method of isolating sources of variance in parametric data

Method to selectively identify reliability risk die based on charac...

Optimization of die yield in a silicon wafer "sweet spot"

Method for analyzing manufacturing data