David A. Byrd

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Puyallup, WA, US

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Patents Grantslast 30 patents

Information Patent Grant
High yielding, voltage, temperature, and process insensitive latera...
- Patent number 7,545,665
- Issue date Jun 9, 2009
- Glacier Microelectronics, Inc.
- Thomas M. Luich
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronically erasable memory cell using CMOS technology
- Patent number 6,528,842
- Issue date Mar 4, 2003
- Jet City Electronics, Inc.
- Thomas M. Luich
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase lock loop with selectable frequency switching time
- Patent number 5,420,545
- Issue date May 30, 1995
- National Semiconductor Corporation
- Craig M. Davis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase-locked loop with automatic phase offset calibration
- Patent number 5,166,641
- Issue date Nov 24, 1992
- National Semiconductor Corporation
- Craig M. Davis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital phase comparator/charge pump with zero deadband and minimum...
- Patent number 4,814,726
- Issue date Mar 21, 1989
- National Semiconductor Corporation
- David A. Byrd
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
High yielding, voltage, temperature, and process insensitive latera...
- Publication number 20090213678
- Publication date Aug 27, 2009
- Thomas M. Luich
- G11 - INFORMATION STORAGE
Information Patent Application
High yielding, voltage, temperature, and process insensitive latera...
- Publication number 20080055959
- Publication date Mar 6, 2008
- Thomas M. Luich
- G11 - INFORMATION STORAGE