David A. Luick

Person

Rochester, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Scheduling instructions in a cascaded delayed execution pipeline to...
- Patent number 8,812,822
- Issue date Aug 19, 2014
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cascaded delayed float/vector execution pipeline
- Patent number 8,756,404
- Issue date Jun 17, 2014
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache line use history based done bit modification to D-cache repla...
- Patent number 8,429,350
- Issue date Apr 23, 2013
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache line use history based done bit modification to I-cache repla...
- Patent number 8,332,587
- Issue date Dec 11, 2012
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Predicated issue for conditional branch instructions
- Patent number 8,301,871
- Issue date Oct 30, 2012
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache line use history based done bit modification to D-cache repla...
- Patent number 8,291,169
- Issue date Oct 16, 2012
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalar precision float implementation on the “W” lane of vector unit
- Patent number 8,169,439
- Issue date May 1, 2012
- International Business Machines Corporation
- David Arnold Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
D-cache line use history based done bit based on successful prefetc...
- Patent number 8,171,224
- Issue date May 1, 2012
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Store misaligned vector with permute
- Patent number 8,161,271
- Issue date Apr 17, 2012
- International Business Machines Corporation
- David Arnold Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
I-cache line use history based done bit based on successful prefetc...
- Patent number 8,140,760
- Issue date Mar 20, 2012
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multithreaded processor and method for switching threads by swappin...
- Patent number 8,140,829
- Issue date Mar 20, 2012
- International Business Machines Corporation
- Richard James Eickemeyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector morphing mechanism for multiple processor cores
- Patent number 8,135,941
- Issue date Mar 13, 2012
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for a group priority issue schema for a cascaded...
- Patent number 8,108,654
- Issue date Jan 31, 2012
- International Business Machines Corporation
- Jeffrey P. Bradford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for optimization within a group priority issue sc...
- Patent number 8,095,779
- Issue date Jan 10, 2012
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3-dimensional L2/L3 cache array to hide translation (TLB) delays
- Patent number 8,019,968
- Issue date Sep 13, 2011
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self prefetching L3/L4 cache mechanism
- Patent number 8,019,969
- Issue date Sep 13, 2011
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure for a single shared instruction predecoder for supporting...
- Patent number 8,001,361
- Issue date Aug 16, 2011
- International Business Machines Corporation
- David Arnold Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiport execution target delay queue FIFO array
- Patent number 7,996,655
- Issue date Aug 9, 2011
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for optimization within a group priority issue sc...
- Patent number 7,996,654
- Issue date Aug 9, 2011
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design structure for single hot forward interconnect scheme for del...
- Patent number 7,984,272
- Issue date Jul 19, 2011
- International Business Machines Corporation
- David Arnold Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for prioritizing arithmetic instructions
- Patent number 7,984,270
- Issue date Jul 19, 2011
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single shared instruction predecoder for supporting multiple proces...
- Patent number 7,945,763
- Issue date May 17, 2011
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Local and global branch prediction information storage
- Patent number 7,941,654
- Issue date May 10, 2011
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for accessing a cache with an effective address
- Patent number 7,937,530
- Issue date May 3, 2011
- International Business Machines Corporation
- David Arnold Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for the scheduling of load instructions within a...
- Patent number 7,882,335
- Issue date Feb 1, 2011
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for prioritizing compare instructions
- Patent number 7,877,579
- Issue date Jan 25, 2011
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for prioritizing branch instructions
- Patent number 7,870,368
- Issue date Jan 11, 2011
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to extend the number of instruction bits in pr...
- Patent number 7,865,699
- Issue date Jan 4, 2011
- International Business Machines Corporation
- Erik R Altman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In situ register state error recovery and restart mechanism
- Patent number 7,865,769
- Issue date Jan 4, 2011
- International Business Machines Corporation
- David Arnold Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for prioritizing store instructions
- Patent number 7,865,700
- Issue date Jan 4, 2011
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PREDICATED ISSUE FOR CONDITIONAL BRANCH INSTRUCTIONS
- Publication number 20120210107
- Publication date Aug 16, 2012
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE LINE USE HISTORY BASED DONE BIT MODIFICATION TO D-CACHE REPLA...
- Publication number 20120159075
- Publication date Jun 21, 2012
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
I-CACHE LINE USE HISTORY BASED DONE BIT BASED ON SUCCESSFUL PREFETC...
- Publication number 20100306472
- Publication date Dec 2, 2010
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE LINE USE HISTORY BASED DONE BIT MODIFICATION TO D-CACHE REPLA...
- Publication number 20100306473
- Publication date Dec 2, 2010
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
D-CACHE LINE USE HISTORY BASED DONE BIT BASED ON SUCCESSFUL PREFETC...
- Publication number 20100306471
- Publication date Dec 2, 2010
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE LINE USE HISTORY BASED DONE BIT MODIFICATION TO I-CACHE REPLA...
- Publication number 20100306474
- Publication date Dec 2, 2010
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Processor Core Vector Morph Coupling Mechanism
- Publication number 20100077177
- Publication date Mar 25, 2010
- International Business Machines Corporation
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiport Execution Target Delay Queue Fifo Array
- Publication number 20090265527
- Publication date Oct 22, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Resolving Issue Conflicts of Load Instructions
- Publication number 20090210666
- Publication date Aug 20, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Optimization Within a Group Priority Issue Sc...
- Publication number 20090210667
- Publication date Aug 20, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Prioritizing Branch Instructions
- Publication number 20090210674
- Publication date Aug 20, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Optimization Within a Group Priority Issue Sc...
- Publication number 20090210677
- Publication date Aug 20, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3-Dimensional L2/L3 Cache Array to Hide Translation (TLB) Delays
- Publication number 20090210624
- Publication date Aug 20, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Issue Schema for a Cascaded Pipeline
- Publication number 20090210664
- Publication date Aug 20, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for a Group Priority Issue Schema for a Cascaded...
- Publication number 20090210665
- Publication date Aug 20, 2009
- Jeffrey P. Bradford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Prioritizing Compare Instructions
- Publication number 20090210673
- Publication date Aug 20, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Prioritizing Floating-Point Instructions
- Publication number 20090210669
- Publication date Aug 20, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Prioritizing Store Instructions
- Publication number 20090210671
- Publication date Aug 20, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Self Prefetching L3/L4 Cache Mechanism
- Publication number 20090210625
- Publication date Aug 20, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Optimization Within a Group Priority Issue Sc...
- Publication number 20090210668
- Publication date Aug 20, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Prioritizing Arithmetic Instructions
- Publication number 20090210670
- Publication date Aug 20, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for the Scheduling of Load Instructions Within a...
- Publication number 20090210676
- Publication date Aug 20, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Resolving Issue Conflicts of Load Instructions
- Publication number 20090210672
- Publication date Aug 20, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Butterfly Physical Chip Floorplan to Allow an ILP Core Polymorphism...
- Publication number 20090204787
- Publication date Aug 13, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Compound Instruction Group Formation and Execution
- Publication number 20090204791
- Publication date Aug 13, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalar Processor Instruction Level Parallelism (ILP) Coupled Pair M...
- Publication number 20090204792
- Publication date Aug 13, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOCAL AND GLOBAL BRANCH PREDICTION INFORMATION STORAGE
- Publication number 20090138690
- Publication date May 28, 2009
- David A. Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalar Float Register Overlay on Vector Register File for Efficient...
- Publication number 20090106526
- Publication date Apr 23, 2009
- David Arnold Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN STRUCTURE FOR SCALAR PRECISION FLOAT IMPLEMENTATION ON THE "...
- Publication number 20090106525
- Publication date Apr 23, 2009
- David Arnold Luick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalar Precision Float Implementation on the "W" Lane of Vector Unit
- Publication number 20090106527
- Publication date Apr 23, 2009
- David Arnold Luick
- G06 - COMPUTING CALCULATING COUNTING

David A. Luick

Person

Patents Grantslast 30 patents

Scheduling instructions in a cascaded delayed execution pipeline to...

Cascaded delayed float/vector execution pipeline

Cache line use history based done bit modification to D-cache repla...

Cache line use history based done bit modification to I-cache repla...

Predicated issue for conditional branch instructions

Cache line use history based done bit modification to D-cache repla...

Scalar precision float implementation on the “W” lane of vector unit

D-cache line use history based done bit based on successful prefetc...

Store misaligned vector with permute

I-cache line use history based done bit based on successful prefetc...

Multithreaded processor and method for switching threads by swappin...

Vector morphing mechanism for multiple processor cores

System and method for a group priority issue schema for a cascaded...

System and method for optimization within a group priority issue sc...

3-dimensional L2/L3 cache array to hide translation (TLB) delays

Self prefetching L3/L4 cache mechanism

Structure for a single shared instruction predecoder for supporting...

Multiport execution target delay queue FIFO array

System and method for optimization within a group priority issue sc...

Design structure for single hot forward interconnect scheme for del...

System and method for prioritizing arithmetic instructions

Single shared instruction predecoder for supporting multiple proces...

Local and global branch prediction information storage

Method and apparatus for accessing a cache with an effective address

System and method for the scheduling of load instructions within a...

System and method for prioritizing compare instructions

System and method for prioritizing branch instructions

Method and apparatus to extend the number of instruction bits in pr...

In situ register state error recovery and restart mechanism

System and method for prioritizing store instructions

Patents Applicationslast 30 patents

PREDICATED ISSUE FOR CONDITIONAL BRANCH INSTRUCTIONS

CACHE LINE USE HISTORY BASED DONE BIT MODIFICATION TO D-CACHE REPLA...

I-CACHE LINE USE HISTORY BASED DONE BIT BASED ON SUCCESSFUL PREFETC...

CACHE LINE USE HISTORY BASED DONE BIT MODIFICATION TO D-CACHE REPLA...

D-CACHE LINE USE HISTORY BASED DONE BIT BASED ON SUCCESSFUL PREFETC...

CACHE LINE USE HISTORY BASED DONE BIT MODIFICATION TO I-CACHE REPLA...

Multiple Processor Core Vector Morph Coupling Mechanism

Multiport Execution Target Delay Queue Fifo Array

System and Method for Resolving Issue Conflicts of Load Instructions

System and Method for Optimization Within a Group Priority Issue Sc...

System and Method for Prioritizing Branch Instructions

System and Method for Optimization Within a Group Priority Issue Sc...

3-Dimensional L2/L3 Cache Array to Hide Translation (TLB) Delays

System and Method for Issue Schema for a Cascaded Pipeline

System and Method for a Group Priority Issue Schema for a Cascaded...

System and Method for Prioritizing Compare Instructions

System and Method for Prioritizing Floating-Point Instructions

System and Method for Prioritizing Store Instructions

Self Prefetching L3/L4 Cache Mechanism

System and Method for Optimization Within a Group Priority Issue Sc...

System and Method for Prioritizing Arithmetic Instructions

System and Method for the Scheduling of Load Instructions Within a...

System and Method for Resolving Issue Conflicts of Load Instructions

Butterfly Physical Chip Floorplan to Allow an ILP Core Polymorphism...

Compound Instruction Group Formation and Execution

Scalar Processor Instruction Level Parallelism (ILP) Coupled Pair M...

LOCAL AND GLOBAL BRANCH PREDICTION INFORMATION STORAGE

Scalar Float Register Overlay on Vector Register File for Efficient...

DESIGN STRUCTURE FOR SCALAR PRECISION FLOAT IMPLEMENTATION ON THE "...

Scalar Precision Float Implementation on the "W" Lane of Vector Unit