David A. Papa

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Automatically routing super-compute interconnects
- Patent number 8,856,495
- Issue date Oct 7, 2014
- International Business Machines Corporation
- Wael R. El-Essawy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Automatically routing super-compute interconnects
- Patent number 8,850,163
- Issue date Sep 30, 2014
- International Business Machines Corporation
- Wael R. El-Essawy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Minimizing the maximum required link capacity for three-dimensional...
- Patent number 8,725,483
- Issue date May 13, 2014
- International Business Machines Corporation
- Wael R. Ei-Essawy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch clustering with proximity to local clock buffers
- Patent number 8,677,299
- Issue date Mar 18, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock optimization with local clock buffer control optimization
- Patent number 8,667,441
- Issue date Mar 4, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoupling capacitor insertion using hypergraph connectivity analysis
- Patent number 8,479,136
- Issue date Jul 2, 2013
- International Business Machines Corporation
- Jeremy T. Hopkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch clustering with proximity to local clock buffers
- Patent number 8,458,634
- Issue date Jun 4, 2013
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accuracy pin-slew mode for gate delay calculation
- Patent number 8,418,108
- Issue date Apr 9, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for bounded transactional timing analysis
- Patent number 8,141,017
- Issue date Mar 20, 2012
- International Business Machines Corporation
- David Papa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimal timing-driven cloning under linear delay model
- Patent number 8,015,532
- Issue date Sep 6, 2011
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for incremental, timing-driven, physical-synthesis optimizat...
- Patent number 7,761,832
- Issue date Jul 20, 2010
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental timing-driven, physical-synthesis using discrete optimi...
- Patent number 7,707,530
- Issue date Apr 27, 2010
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Automatically Routing Super-Compute Interconnects
- Publication number 20130031270
- Publication date Jan 31, 2013
- International Business Machines Corporation
- Wael R. El-Essawy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatically Routing Super-Compute Interconnects
- Publication number 20130031334
- Publication date Jan 31, 2013
- International Business Machines Corporation
- Wael R. El-Essawy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCURACY PIN-SLEW MODE FOR GATE DELAY CALCULATION
- Publication number 20120324409
- Publication date Dec 20, 2012
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DECOUPLING CAPACITOR INSERTION USING HYPERGRAPH CONNECTIVITY ANALYSIS
- Publication number 20120284676
- Publication date Nov 8, 2012
- International Business Machines Corporation
- Jeremy T. Hopkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Minimizing the Maximum Required Link Capacity for Three-Dimensional...
- Publication number 20120185216
- Publication date Jul 19, 2012
- International Business Machines Corporation
- Wael R. El-Essawy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Optimization with Local Clock Buffer Control Optimization
- Publication number 20120124539
- Publication date May 17, 2012
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LATCH CLUSTERING WITH PROXIMITY TO LOCAL CLOCK BUFFERS
- Publication number 20120110532
- Publication date May 3, 2012
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Bounded Transactional Timing Analysis
- Publication number 20100077368
- Publication date Mar 25, 2010
- International Business Machines Corporation
- David Papa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR INCREMENTAL, TIMING-DRIVEN, PHYSICAL-SYNTHESIS OPTIMIZAT...
- Publication number 20090132970
- Publication date May 21, 2009
- CHARLES J. ALPERT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Incremental, Timing-Driven, Physical-Synthesis Using Dis...
- Publication number 20090132981
- Publication date May 21, 2009
- CHARLES J. ALPERT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods for Optimal Timing-Driven Cloning Under Linear Delay Model
- Publication number 20090125859
- Publication date May 14, 2009
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR INCREMENTAL, TIMING-DRIVEN, PHYSICAL-SYNTHESIS OPTIMIZATION
- Publication number 20090089721
- Publication date Apr 2, 2009
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING

David A. Papa

Person

Patents Grantslast 30 patents

Automatically routing super-compute interconnects

Automatically routing super-compute interconnects

Minimizing the maximum required link capacity for three-dimensional...

Latch clustering with proximity to local clock buffers

Clock optimization with local clock buffer control optimization

Decoupling capacitor insertion using hypergraph connectivity analysis

Latch clustering with proximity to local clock buffers

Accuracy pin-slew mode for gate delay calculation

Method for bounded transactional timing analysis

Optimal timing-driven cloning under linear delay model

Method for incremental, timing-driven, physical-synthesis optimizat...

Incremental timing-driven, physical-synthesis using discrete optimi...

Patents Applicationslast 30 patents

Automatically Routing Super-Compute Interconnects

Automatically Routing Super-Compute Interconnects

ACCURACY PIN-SLEW MODE FOR GATE DELAY CALCULATION

DECOUPLING CAPACITOR INSERTION USING HYPERGRAPH CONNECTIVITY ANALYSIS

Minimizing the Maximum Required Link Capacity for Three-Dimensional...

Clock Optimization with Local Clock Buffer Control Optimization

LATCH CLUSTERING WITH PROXIMITY TO LOCAL CLOCK BUFFERS

Method for Bounded Transactional Timing Analysis

METHOD FOR INCREMENTAL, TIMING-DRIVEN, PHYSICAL-SYNTHESIS OPTIMIZAT...

Method for Incremental, Timing-Driven, Physical-Synthesis Using Dis...

Methods for Optimal Timing-Driven Cloning Under Linear Delay Model

METHOD FOR INCREMENTAL, TIMING-DRIVEN, PHYSICAL-SYNTHESIS OPTIMIZATION