David Asher

Person

Sutton, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Processor data cache with shared mid-level cache and low-level cache
- Patent number 12,210,457
- Issue date Jan 28, 2025
- Marvell Asia Pte, Ltd.
- Shubhendu S. Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low latency inter-chip communication mechanism in a multi-chip proc...
- Patent number 12,019,552
- Issue date Jun 25, 2024
- Marvell Asia Pte, Ltd.
- Craig Barner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for distributing memory requests
- Patent number 11,868,262
- Issue date Jan 9, 2024
- Marvell Asia Pte, Ltd.
- Richard E. Kessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low latency inter-chip communication mechanism in a multi-chip proc...
- Patent number 11,620,223
- Issue date Apr 4, 2023
- Marvell Asia Pte, Ltd.
- Craig Barner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for distributing memory requests
- Patent number 11,615,027
- Issue date Mar 28, 2023
- Marvell Asia Pte, Ltd.
- Richard E. Kessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Differential cache block sizing for computing systems
- Patent number 11,379,379
- Issue date Jul 5, 2022
- Marvell Asia Pte, Ltd.
- Shubhendu Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing low-level instructions and core interactions in multi-core...
- Patent number 11,327,759
- Issue date May 10, 2022
- Marvell Asia Pte, Ltd.
- David Albert Carlson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for distributing memory requests
- Patent number 11,188,466
- Issue date Nov 30, 2021
- Marvell Asia Pte, Ltd.
- Richard E. Kessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low latency inter-chip communication mechanism in multi-chip proces...
- Patent number 11,119,929
- Issue date Sep 14, 2021
- Marvell Asia Pte, Ltd.
- Craig Barner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared mid-level data cache
- Patent number 11,093,405
- Issue date Aug 17, 2021
- Marvell Asia Pte, Ltd.
- Shubhendu S. Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mid-level instruction cache
- Patent number 11,036,643
- Issue date Jun 15, 2021
- Marvell Asia Pte, Ltd.
- David H. Asher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing lock and unlock operations using operation prediction
- Patent number 10,599,430
- Issue date Mar 24, 2020
- Cavium, LLC
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for distributing memory requests
- Patent number 10,558,573
- Issue date Feb 11, 2020
- Cavium, LLC
- Richard E. Kessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing lock and unlock operations using traffic prioritization
- Patent number 10,445,096
- Issue date Oct 15, 2019
- Cavium, LLC
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing fairness for lock and unlock operations using operation pr...
- Patent number 10,331,500
- Issue date Jun 25, 2019
- Cavium, LLC
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing cache partitions based on cache usage information
- Patent number 10,282,299
- Issue date May 7, 2019
- Cavium, LLC
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing lock and unlock operations using active spinning
- Patent number 10,248,420
- Issue date Apr 2, 2019
- Cavium, LLC
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for determining metric for selective caching
- Patent number 10,007,614
- Issue date Jun 26, 2018
- Cavium, Inc.
- Xiaodong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification of a multichip coherence protocol
- Patent number 10,002,218
- Issue date Jun 19, 2018
- Cavium, Inc.
- Shahid Ikram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing buffered communication between cores
- Patent number 9,870,328
- Issue date Jan 16, 2018
- Cavium, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing buffered communication between sockets
- Patent number 9,665,505
- Issue date May 30, 2017
- Cavium, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network processor with distributed trace buffers
- Patent number 9,612,934
- Issue date Apr 4, 2017
- Cavium, Inc.
- Bradley D. Dobbie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translation lookaside buffer management
- Patent number 9,501,425
- Issue date Nov 22, 2016
- Cavium, Inc.
- Shubhendu S. Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for conditional storing of data using a compar...
- Patent number 9,390,023
- Issue date Jul 12, 2016
- Cavium, Inc.
- Richard E. Kessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inter-chip interconnect protocol for a multi-chip system
- Patent number 9,372,800
- Issue date Jun 21, 2016
- Cavium, Inc.
- Isam Akkawi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for automated functional coverage generation and...
- Patent number 9,355,206
- Issue date May 31, 2016
- Cavium, Inc.
- Shahid Ikram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-core interconnect in a network processor
- Patent number 9,330,002
- Issue date May 3, 2016
- Cavium, Inc.
- Richard E. Kessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for managing write back cache
- Patent number 9,141,548
- Issue date Sep 22, 2015
- Cavium, Inc.
- David H. Asher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for specifying. modeling, implementing and veri...
- Patent number 9,058,463
- Issue date Jun 16, 2015
- Cavium, Inc.
- Shahid Ikram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Input output bridging
- Patent number 8,595,401
- Issue date Nov 26, 2013
- Cavium, Inc.
- Robert A. Sanzone
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LOW LATENCY INTER-CHIP COMMUNICATION MECHANISM IN A MULTI-CHIP PROC...
- Publication number 20230229595
- Publication date Jul 20, 2023
- Marvell Asia Pte, Ltd.
- Craig BARNER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR DISTRIBUTING MEMORY REQUESTS
- Publication number 20230185720
- Publication date Jun 15, 2023
- Marvell Asia Pte, Ltd.
- Richard E. KESSLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR DISTRIBUTING MEMORY REQUESTS
- Publication number 20220114101
- Publication date Apr 14, 2022
- Marvell Asia Pte, Ltd.
- Richard E. KESSLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LATENCY INTER-CHIP COMMUNICATION MECHANISM IN A MULTI-CHIP PROC...
- Publication number 20210374057
- Publication date Dec 2, 2021
- Marvell Asia Pte, Ltd.
- Craig BARNER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LATENCY INTER-CHIP COMMUNICATION MECHANISM IN MULTI-CHIP PROCES...
- Publication number 20200250088
- Publication date Aug 6, 2020
- Cavium LLC
- Craig Barner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR DISTRIBUTING MEMORY REQUESTS
- Publication number 20200183844
- Publication date Jun 11, 2020
- Marvell Semiconductor, Inc.
- Richard E. KESSLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING LOW-LEVEL INSTRUCTIONS AND CORE INTERACTIONS IN MULTI-CORE...
- Publication number 20200097292
- Publication date Mar 26, 2020
- Marvell International Ltd.
- David Albert Carlson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING CACHE PARTITIONS BASED ON CACHE USAGE INFORMATION
- Publication number 20180373635
- Publication date Dec 27, 2018
- Cavium, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING LOCK AND UNLOCK OPERATIONS USING TRAFFIC PRIORITIZATION
- Publication number 20180293100
- Publication date Oct 11, 2018
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING LOCK AND UNLOCK OPERATIONS USING OPERATION PREDICTION
- Publication number 20180293070
- Publication date Oct 11, 2018
- Cavium, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING LOCK AND UNLOCK OPERATIONS USING ACTIVE SPINNING
- Publication number 20180293113
- Publication date Oct 11, 2018
- Cavium, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING FAIRNESS FOR LOCK AND UNLOCK OPERATIONS USING OPERATION PR...
- Publication number 20180293114
- Publication date Oct 11, 2018
- Cavium, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DETERMINING METRIC FOR SELECTIVE CACHING
- Publication number 20170220477
- Publication date Aug 3, 2017
- Cavium, Inc.
- Xiaodong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN AND VERIFICATION OF A MULTICHIP COHERENCE PROTOCOL
- Publication number 20160267209
- Publication date Sep 15, 2016
- Cavium, Inc.
- Shahid Ikram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING BUFFERED COMMUNICATION BETWEEN SOCKETS
- Publication number 20160140060
- Publication date May 19, 2016
- Cavium, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING BUFFERED COMMUNICATION BETWEEN CORES
- Publication number 20160140061
- Publication date May 19, 2016
- Cavium, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSLATION LOOKASIDE BUFFER MANAGEMENT
- Publication number 20160140047
- Publication date May 19, 2016
- Cavium, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR AUTOMATED FUNCTIONAL COVERAGE GENERATION AN...
- Publication number 20150302133
- Publication date Oct 22, 2015
- Cavium, Inc.
- Shahid Ikram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CORE NETWORK PROCESSOR INTERCONNECT WITH MULTI-NODE CONNECTION
- Publication number 20150254182
- Publication date Sep 10, 2015
- Cavium, Inc.
- David H. Asher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTER-CHIP INTERCONNECT PROTOCOL FOR A MULTI-CHIP SYSTEM
- Publication number 20150254183
- Publication date Sep 10, 2015
- Cavium, Inc.
- Isam Akkawi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR SPECIFYING. MODELING, IMPLEMENTING AND VERI...
- Publication number 20150154341
- Publication date Jun 4, 2015
- Cavium, Inc.
- Shahid Ikram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method And Apparatus For Conditional Storing Of Data Using A Compar...
- Publication number 20150100737
- Publication date Apr 9, 2015
- Cavium, Inc.
- Richard E. Kessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Managing Write Back Cache
- Publication number 20140317353
- Publication date Oct 23, 2014
- Cavium, Inc.
- David H. Asher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Input Output Bridging
- Publication number 20130282942
- Publication date Oct 24, 2013
- Robert A. Sanzone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK PROCESSOR WITH DISTRIBUTED TRACE BUFFERS
- Publication number 20130111073
- Publication date May 2, 2013
- Cavium, Inc.
- Bradley D. Dobbie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CORE INTERCONNECT IN A NETWORK PROCESSOR
- Publication number 20130111141
- Publication date May 2, 2013
- Cavium, Inc.
- Richard E. Kessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INPUT OUTPUT BRIDGING
- Publication number 20130103870
- Publication date Apr 25, 2013
- Cavium, Inc.
- Robert A. Sanzone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Store instruction ordering for multi-core processor
- Publication number 20060095741
- Publication date May 4, 2006
- Cavium Networks
- David H. Asher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for managing write back cache
- Publication number 20060059316
- Publication date Mar 16, 2006
- Cavium Networks
- David H. Asher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Local scratchpad and data caching system
- Publication number 20060059310
- Publication date Mar 16, 2006
- Cavium Networks
- David H. Asher
- G06 - COMPUTING CALCULATING COUNTING

David Asher

Person

Patents Grantslast 30 patents

Processor data cache with shared mid-level cache and low-level cache

Low latency inter-chip communication mechanism in a multi-chip proc...

Methods and systems for distributing memory requests

Low latency inter-chip communication mechanism in a multi-chip proc...

Methods and systems for distributing memory requests

Differential cache block sizing for computing systems

Managing low-level instructions and core interactions in multi-core...

Methods and systems for distributing memory requests

Low latency inter-chip communication mechanism in multi-chip proces...

Shared mid-level data cache

Mid-level instruction cache

Managing lock and unlock operations using operation prediction

Methods and systems for distributing memory requests

Managing lock and unlock operations using traffic prioritization

Managing fairness for lock and unlock operations using operation pr...

Managing cache partitions based on cache usage information

Managing lock and unlock operations using active spinning

Method and apparatus for determining metric for selective caching

Verification of a multichip coherence protocol

Managing buffered communication between cores

Managing buffered communication between sockets

Network processor with distributed trace buffers

Translation lookaside buffer management

Method and apparatus for conditional storing of data using a compar...

Inter-chip interconnect protocol for a multi-chip system

System and method for automated functional coverage generation and...

Multi-core interconnect in a network processor

Method and apparatus for managing write back cache

Systems and methods for specifying. modeling, implementing and veri...

Input output bridging

Patents Applicationslast 30 patents

LOW LATENCY INTER-CHIP COMMUNICATION MECHANISM IN A MULTI-CHIP PROC...

METHODS AND SYSTEMS FOR DISTRIBUTING MEMORY REQUESTS

METHODS AND SYSTEMS FOR DISTRIBUTING MEMORY REQUESTS

LOW LATENCY INTER-CHIP COMMUNICATION MECHANISM IN A MULTI-CHIP PROC...

LOW LATENCY INTER-CHIP COMMUNICATION MECHANISM IN MULTI-CHIP PROCES...

METHODS AND SYSTEMS FOR DISTRIBUTING MEMORY REQUESTS

MANAGING LOW-LEVEL INSTRUCTIONS AND CORE INTERACTIONS IN MULTI-CORE...

MANAGING CACHE PARTITIONS BASED ON CACHE USAGE INFORMATION

MANAGING LOCK AND UNLOCK OPERATIONS USING TRAFFIC PRIORITIZATION

MANAGING LOCK AND UNLOCK OPERATIONS USING OPERATION PREDICTION

MANAGING LOCK AND UNLOCK OPERATIONS USING ACTIVE SPINNING

MANAGING FAIRNESS FOR LOCK AND UNLOCK OPERATIONS USING OPERATION PR...

METHOD AND APPARATUS FOR DETERMINING METRIC FOR SELECTIVE CACHING

DESIGN AND VERIFICATION OF A MULTICHIP COHERENCE PROTOCOL

MANAGING BUFFERED COMMUNICATION BETWEEN SOCKETS

MANAGING BUFFERED COMMUNICATION BETWEEN CORES

TRANSLATION LOOKASIDE BUFFER MANAGEMENT

SYSTEMS AND METHODS FOR AUTOMATED FUNCTIONAL COVERAGE GENERATION AN...

MULTI-CORE NETWORK PROCESSOR INTERCONNECT WITH MULTI-NODE CONNECTION

INTER-CHIP INTERCONNECT PROTOCOL FOR A MULTI-CHIP SYSTEM

SYSTEMS AND METHODS FOR SPECIFYING. MODELING, IMPLEMENTING AND VERI...

Method And Apparatus For Conditional Storing Of Data Using A Compar...

Method and Apparatus for Managing Write Back Cache

Input Output Bridging

NETWORK PROCESSOR WITH DISTRIBUTED TRACE BUFFERS

MULTI-CORE INTERCONNECT IN A NETWORK PROCESSOR

INPUT OUTPUT BRIDGING

Store instruction ordering for multi-core processor

Method and apparatus for managing write back cache

Local scratchpad and data caching system