David B. Witt

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Microprocessor with non-cacheable memory load prediction
- Patent number 12,141,580
- Issue date Nov 12, 2024
- Simplex Micro, Inc.
- David Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
General purpose register file architecture for aligned simd
- Patent number 7,120,781
- Issue date Oct 10, 2006
- Intel Corporation
- Ravi Kolagotla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined processor including a loosely coupled side pipe
- Patent number 6,918,028
- Issue date Jul 12, 2005
- Analog Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modulo address generation method and apparatus
- Patent number 6,584,556
- Issue date Jun 24, 2003
- Analog Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Universal dependency vector/queue entry
- Patent number 6,553,482
- Issue date Apr 22, 2003
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor including efficient fetch mechanism for L0 and L1 caches
- Patent number 6,505,292
- Issue date Jan 7, 2003
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor configured to predecode relative control transfer instruc...
- Patent number 6,457,117
- Issue date Sep 24, 2002
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System having a configurable cache/SRAM memory
- Patent number 6,446,181
- Issue date Sep 3, 2002
- Intel Corporation
- Hebbalalu S. Ramagopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical rename register for efficiently storing floating point, in...
- Patent number 6,393,546
- Issue date May 21, 2002
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction alignment unit for routing variable byte-length instruc...
- Patent number 6,393,549
- Issue date May 21, 2002
- Advanced Micro Devices, Inc.
- Thang Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Line-oriented reorder buffer configured to selectively store a memo...
- Patent number 6,381,689
- Issue date Apr 30, 2002
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor including efficient fetch mechanism for L0 and L1 caches
- Patent number 6,367,001
- Issue date Apr 2, 2002
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and circuit for single cycle multiple branch history table a...
- Patent number 6,347,369
- Issue date Feb 12, 2002
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cumulative lookahead to eliminate chained dependencies
- Patent number 6,332,187
- Issue date Dec 18, 2001
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for canceling speculatively fetched instructions following a...
- Patent number 6,332,191
- Issue date Dec 18, 2001
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch instruction specifying destination functional unit and rea...
- Patent number 6,321,326
- Issue date Nov 20, 2001
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction queue evaluating dependency vector in portions during d...
- Patent number 6,308,259
- Issue date Oct 23, 2001
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance load/store functional unit and data cache
- Patent number 6,298,423
- Issue date Oct 2, 2001
- Advanced Micro Devices, Inc.
- William M. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reorder buffer employing last in line indication
- Patent number 6,292,884
- Issue date Sep 18, 2001
- Advanced Micro Devices, Inc.
- Thang M. Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction decoder/dispatch
- Patent number 6,279,101
- Issue date Aug 21, 2001
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reverse TLB for providing branch target address in a microprocessor...
- Patent number 6,266,752
- Issue date Jul 24, 2001
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical rename register for efficiently storing floating point, in...
- Patent number 6,266,763
- Issue date Jul 24, 2001
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor configured to selectively cancel instructions from its pi...
- Patent number 6,256,728
- Issue date Jul 3, 2001
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register renaming in which moves are accomplished by swapping tags
- Patent number 6,256,721
- Issue date Jul 3, 2001
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor configured to map logical register numbers to physical re...
- Patent number 6,247,106
- Issue date Jun 12, 2001
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cumulative lookahead to eliminate chained dependencies
- Patent number 6,240,503
- Issue date May 29, 2001
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Linearly addressable microprocessor cache
- Patent number 6,240,484
- Issue date May 29, 2001
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reorder buffer configured to allocate storage for instruction resul...
- Patent number 6,237,082
- Issue date May 22, 2001
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor configured to selectively free physical registers upon re...
- Patent number 6,230,262
- Issue date May 8, 2001
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor with N adders for parallel target addresses calculation
- Patent number 6,219,784
- Issue date Apr 17, 2001
- Advanced Micro Devices, Inc.
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MICROPROCESSOR WITH NON-CACHEABLE MEMORY LOAD PREDICTION
- Publication number 20230342148
- Publication date Oct 26, 2023
- Simplex Micro, Inc.
- David Witt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for hazard detection and management in a pipel...
- Publication number 20040158694
- Publication date Aug 12, 2004
- Thomas J. Tomazin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital signal processor architecture for high computation speed
- Publication number 20030196072
- Publication date Oct 16, 2003
- Murali S. Chinnakonda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Line-oriented reorder buffer
- Publication number 20020007450
- Publication date Jan 17, 2002
- David B. Witt
- G06 - COMPUTING CALCULATING COUNTING

David B. Witt

Person

Patents Grantslast 30 patents

Microprocessor with non-cacheable memory load prediction

General purpose register file architecture for aligned simd

Pipelined processor including a loosely coupled side pipe

Modulo address generation method and apparatus

Universal dependency vector/queue entry

Processor including efficient fetch mechanism for L0 and L1 caches

Processor configured to predecode relative control transfer instruc...

System having a configurable cache/SRAM memory

Physical rename register for efficiently storing floating point, in...

Instruction alignment unit for routing variable byte-length instruc...

Line-oriented reorder buffer configured to selectively store a memo...

Processor including efficient fetch mechanism for L0 and L1 caches

Method and circuit for single cycle multiple branch history table a...

Cumulative lookahead to eliminate chained dependencies

System for canceling speculatively fetched instructions following a...

Prefetch instruction specifying destination functional unit and rea...

Instruction queue evaluating dependency vector in portions during d...

High performance load/store functional unit and data cache

Reorder buffer employing last in line indication

Instruction decoder/dispatch

Reverse TLB for providing branch target address in a microprocessor...

Physical rename register for efficiently storing floating point, in...

Processor configured to selectively cancel instructions from its pi...

Register renaming in which moves are accomplished by swapping tags

Processor configured to map logical register numbers to physical re...

Cumulative lookahead to eliminate chained dependencies

Linearly addressable microprocessor cache

Reorder buffer configured to allocate storage for instruction resul...

Processor configured to selectively free physical registers upon re...

Processor with N adders for parallel target addresses calculation

Patents Applicationslast 30 patents

MICROPROCESSOR WITH NON-CACHEABLE MEMORY LOAD PREDICTION

Method and apparatus for hazard detection and management in a pipel...

Digital signal processor architecture for high computation speed

Line-oriented reorder buffer