David Cashman

Person

Toronto, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Structures for LUT-based arithmetic in PLDs
- Patent number 9,658,830
- Issue date May 23, 2017
- Altera Corporation
- Ketan Padalia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus for providing redundancy on multi-chip devices
- Patent number 9,030,227
- Issue date May 12, 2015
- Altera Corporation
- David Cashman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable integrated circuits with redundant circuitry
- Patent number 8,860,460
- Issue date Oct 14, 2014
- Altera Corporation
- David Cashman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Structures for LUT-based arithmetic in PLDs
- Patent number 8,788,550
- Issue date Jul 22, 2014
- Altera Corporation
- Ketan Padalia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuits with multi-stage logic regions
- Patent number 8,581,624
- Issue date Nov 12, 2013
- Altera Corporation
- David Cashman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Robust time borrowing pulse latches
- Patent number 8,427,213
- Issue date Apr 23, 2013
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and systems for managing a write operation
- Patent number 8,242,806
- Issue date Aug 14, 2012
- Altera Corporation
- David Cashman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable time borrowing flip-flops
- Patent number 8,222,921
- Issue date Jul 17, 2012
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Robust time borrowing pulse latches
- Patent number 8,115,530
- Issue date Feb 14, 2012
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Robust time borrowing pulse latches
- Patent number 7,872,512
- Issue date Jan 18, 2011
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable time borrowing flip-flops
- Patent number 7,868,655
- Issue date Jan 11, 2011
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Staggered logic array block architecture
- Patent number 7,724,031
- Issue date May 25, 2010
- Altera Corporation
- David Cashman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device architectures and methods for implementin...
- Patent number 7,716,623
- Issue date May 11, 2010
- Altera Corporation
- Tim Vanderhoek
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device architectures and methods for implementin...
- Patent number 7,619,443
- Issue date Nov 17, 2009
- Altera Corporation
- Tim Vanderhoek
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable time borrowing flip-flops
- Patent number 7,583,103
- Issue date Sep 1, 2009
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device with configurable override of region-wide...
- Patent number 7,579,866
- Issue date Aug 25, 2009
- Altera Corporation
- Michael D. Hutton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Structures for LUT-based arithmetic in PLDs
- Patent number 7,558,812
- Issue date Jul 7, 2009
- Altera Corporation
- Ketan Padalia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device having redundancy with logic element gran...
- Patent number 7,508,231
- Issue date Mar 24, 2009
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device having logic array block interconnect lin...
- Patent number 7,456,653
- Issue date Nov 25, 2008
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adder circuitry for a programmable logic device
- Patent number 7,268,584
- Issue date Sep 11, 2007
- Altera Corporation
- David Cashman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for enhancing signal routability
- Patent number 7,185,306
- Issue date Feb 27, 2007
- Altera Corporation
- Paul Leventis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device with redundant circuitry
- Patent number 6,965,249
- Issue date Nov 15, 2005
- Altera Corporation
- Christopher Lane
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
STRUCTURES FOR LUT-BASED ARITHMETIC IN PLDS
- Publication number 20170322775
- Publication date Nov 9, 2017
- Altera Corporation
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUITS WITH MULTI-STAGE LOGIC REGIONS
- Publication number 20130257476
- Publication date Oct 3, 2013
- David Cashman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ROBUST TIME BORROWING PULSE LATCHES
- Publication number 20120112791
- Publication date May 10, 2012
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONFIGURABLE TIME BORROWING FLIP-FLOPS
- Publication number 20110102017
- Publication date May 5, 2011
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROBUST TIME BORROWING PULSE LATCHES
- Publication number 20110089974
- Publication date Apr 21, 2011
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONFIGURABLE TIME BORROWING FLIP-FLOPS
- Publication number 20090278566
- Publication date Nov 12, 2009
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROBUST TIME BORROWING PULSE LATCHES
- Publication number 20090243687
- Publication date Oct 1, 2009
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configurable time borrowing flip-flops
- Publication number 20080238476
- Publication date Oct 2, 2008
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Staggered logic array block architecture
- Publication number 20080231317
- Publication date Sep 25, 2008
- Altera Corporation
- David Cashman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE LOGIC DEVICE HAVING REDUNDANCY WITH LOGIC ELEMENT GRAN...
- Publication number 20080218197
- Publication date Sep 11, 2008
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE LOGIC DEVICE HAVING LOGIC ARRAY BLOCK INTERCONNECT LIN...
- Publication number 20080218208
- Publication date Sep 11, 2008
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with redundant circuitry
- Publication number 20030072185
- Publication date Apr 17, 2003
- Christopher Lane
- H03 - BASIC ELECTRONIC CIRCUITRY

David Cashman

Person

Patents Grantslast 30 patents

Structures for LUT-based arithmetic in PLDs

Methods and apparatus for providing redundancy on multi-chip devices

Programmable integrated circuits with redundant circuitry

Structures for LUT-based arithmetic in PLDs

Integrated circuits with multi-stage logic regions

Robust time borrowing pulse latches

Methods and systems for managing a write operation

Configurable time borrowing flip-flops

Robust time borrowing pulse latches

Robust time borrowing pulse latches

Configurable time borrowing flip-flops

Staggered logic array block architecture

Programmable logic device architectures and methods for implementin...

Programmable logic device architectures and methods for implementin...

Configurable time borrowing flip-flops

Programmable logic device with configurable override of region-wide...

Structures for LUT-based arithmetic in PLDs

Programmable logic device having redundancy with logic element gran...

Programmable logic device having logic array block interconnect lin...

Adder circuitry for a programmable logic device

Method and apparatus for enhancing signal routability

Programmable logic device with redundant circuitry

Patents Applicationslast 30 patents

STRUCTURES FOR LUT-BASED ARITHMETIC IN PLDS

INTEGRATED CIRCUITS WITH MULTI-STAGE LOGIC REGIONS

ROBUST TIME BORROWING PULSE LATCHES

CONFIGURABLE TIME BORROWING FLIP-FLOPS

ROBUST TIME BORROWING PULSE LATCHES

CONFIGURABLE TIME BORROWING FLIP-FLOPS

ROBUST TIME BORROWING PULSE LATCHES

Configurable time borrowing flip-flops

Staggered logic array block architecture

PROGRAMMABLE LOGIC DEVICE HAVING REDUNDANCY WITH LOGIC ELEMENT GRAN...

PROGRAMMABLE LOGIC DEVICE HAVING LOGIC ARRAY BLOCK INTERCONNECT LIN...

Programmable logic device with redundant circuitry