David Doman

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method, apparatus, and system for using a cover mask for enabling m...
- Patent number 10,068,806
- Issue date Sep 4, 2018
- GLOBALFOUNDRIES Inc.
- David C. Pritchard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, apparatus, and system for using a cover mask for enabling m...
- Patent number 9,947,590
- Issue date Apr 17, 2018
- GLOBALFOUNDRIES Inc.
- David C. Pritchard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pass-through contact using silicide
- Patent number 9,666,488
- Issue date May 30, 2017
- GLOBALFOUNDRIES Inc.
- Tuhin Guha Neogi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of using a trench salicide routing layer
- Patent number 9,196,548
- Issue date Nov 24, 2015
- GLOBALFOUNDRIES Inc.
- Mahbub Rashed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked power supplies for integrated circuit devices and methods o...
- Patent number 9,147,658
- Issue date Sep 29, 2015
- GLOBALFOUNDRIES Inc.
- David S. Doman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cross-coupling based design using diffusion contact structures
- Patent number 8,987,128
- Issue date Mar 24, 2015
- GLOBALFOUNDRIES Inc.
- Mahbub Rashed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrating optimal planar and three-dimensional semiconductor desi...
- Patent number 8,966,423
- Issue date Feb 24, 2015
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software and method for via spacing in a semiconductor device
- Patent number 8,859,416
- Issue date Oct 14, 2014
- GLOBALFOUNDRIES, INC.
- David S. Doman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Providing timing-closed FinFET designs from planar designs
- Patent number 8,689,154
- Issue date Apr 1, 2014
- GLOBALFOUNDRIES Inc.
- Mahbub Rashed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor devices formed on a continuous active region with an...
- Patent number 8,618,607
- Issue date Dec 31, 2013
- GLOBALFOUNDRIES Inc.
- Mahbub Rashed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having contact layer providing electrical conn...
- Patent number 8,598,633
- Issue date Dec 3, 2013
- GLOBALFOUNDRIES, INC.
- Marc Tarabbia
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR USING A COVER MASK FOR ENABLING M...
- Publication number 20180182674
- Publication date Jun 28, 2018
- GLOBALFOUNDRIES INC.
- David C. Pritchard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR USING A COVER MASK FOR ENABLING M...
- Publication number 20180108571
- Publication date Apr 19, 2018
- GLOBALFOUNDRIES INC.
- David C. Pritchard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATING OPTIMAL PLANAR AND THREE-DIMENSIONAL SEMICONDUCTOR DESI...
- Publication number 20140258960
- Publication date Sep 11, 2014
- GLOBALFOUNDRIES INC.
- Navneet Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS OF USING A TRENCH SALICIDE ROUTING LAYER
- Publication number 20140183638
- Publication date Jul 3, 2014
- GLOBALFOUNDRIES INC.
- Mahbub RASHED
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CROSS-COUPLING BASED DESIGN USING DIFFUSION CONTACT STRUCTURES
- Publication number 20140027918
- Publication date Jan 30, 2014
- GLOBALFOUNDRIES INC.
- Mahbub Rashed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICES FORMED ON A CONTINUOUS ACTIVE REGION WITH AN...
- Publication number 20140001563
- Publication date Jan 2, 2014
- GLOBALFOUNDRIES INC.
- Mahbub Rashed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOFTWARE AND METHOD FOR VIA SPACING IN A SEMICONDUCTOR DEVICE
- Publication number 20130280905
- Publication date Oct 24, 2013
- GLOBALFOUNDRIES INC.
- David S. Doman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROVIDING TIMING-CLOSED FINFET DESIGNS FROM PLANAR DESIGNS
- Publication number 20130275935
- Publication date Oct 17, 2013
- GLOBALFOUNDRIES INC.
- Mahbub Rashed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20130181289
- Publication date Jul 18, 2013
- GLOBALFOUNDRIES INC.
- Marc Tarabbia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacked Power Supplies for Integrated Circuit Devices and Methods o...
- Publication number 20130100590
- Publication date Apr 25, 2013
- GLOBALFOUNDRIES INC.
- David S. Doman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods and Circuits for Achieving Rational Fractional Drive Curren...
- Publication number 20130099856
- Publication date Apr 25, 2013
- GLOBALFOUNDRIES INC.
- David S. Doman
- H01 - BASIC ELECTRIC ELEMENTS

David Doman

Person

Patents Grantslast 30 patents

Method, apparatus, and system for using a cover mask for enabling m...

Method, apparatus, and system for using a cover mask for enabling m...

Pass-through contact using silicide

Methods of using a trench salicide routing layer

Stacked power supplies for integrated circuit devices and methods o...

Cross-coupling based design using diffusion contact structures

Integrating optimal planar and three-dimensional semiconductor desi...

Software and method for via spacing in a semiconductor device

Providing timing-closed FinFET designs from planar designs

Semiconductor devices formed on a continuous active region with an...

Semiconductor device having contact layer providing electrical conn...

Patents Applicationslast 30 patents

METHOD, APPARATUS, AND SYSTEM FOR USING A COVER MASK FOR ENABLING M...

METHOD, APPARATUS, AND SYSTEM FOR USING A COVER MASK FOR ENABLING M...

INTEGRATING OPTIMAL PLANAR AND THREE-DIMENSIONAL SEMICONDUCTOR DESI...

METHODS OF USING A TRENCH SALICIDE ROUTING LAYER

CROSS-COUPLING BASED DESIGN USING DIFFUSION CONTACT STRUCTURES

SEMICONDUCTOR DEVICES FORMED ON A CONTINUOUS ACTIVE REGION WITH AN...

SOFTWARE AND METHOD FOR VIA SPACING IN A SEMICONDUCTOR DEVICE

PROVIDING TIMING-CLOSED FINFET DESIGNS FROM PLANAR DESIGNS

SEMICONDUCTOR DEVICE

Stacked Power Supplies for Integrated Circuit Devices and Methods o...

Methods and Circuits for Achieving Rational Fractional Drive Curren...