David E. Lackey

Person

Jericho, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and device for selectively adding timing margin in an integr...
- Patent number 8,589,843
- Issue date Nov 19, 2013
- International Business Machines Corporation
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Grant
Test path selection and test program generation for performance tes...
- Patent number 8,543,966
- Issue date Sep 24, 2013
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Grant
Method and device for selectively adding timing margin in an integr...
- Patent number 8,504,971
- Issue date Aug 6, 2013
- International Business Machines Corporation
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Grant
Method and device for selectively adding timing margin in an integr...
- Patent number 8,490,045
- Issue date Jul 16, 2013
- International Business Machines Corporation
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Grant
Disposition of integrated circuits using performance sort ring osci...
- Patent number 8,490,040
- Issue date Jul 16, 2013
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Grant
Dense register array for enabling scan out observation of both L1 a...
- Patent number 8,423,844
- Issue date Apr 16, 2013
- International Business Machines Corporation
- Pamela S. Gillis
- G01 - MEASURING TESTING
Information Patent Grant
Microcontroller for logic built-in self test (LBIST)
- Patent number 8,423,847
- Issue date Apr 16, 2013
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for a robust embedded interface
- Patent number 8,239,715
- Issue date Aug 7, 2012
- International Business Machines Corporation
- Steven M. Eustis
- G11 - INFORMATION STORAGE
Information Patent Grant
Microcontroller for logic built-in self test (LBIST)
- Patent number 8,205,124
- Issue date Jun 19, 2012
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
Hold transition fault model and test generation method
- Patent number 8,181,135
- Issue date May 15, 2012
- International Business Machines Corporation
- Vikram Iyengar
- G01 - MEASURING TESTING
Information Patent Grant
Method and device for selectively adding timing margin in an integr...
- Patent number 8,122,409
- Issue date Feb 21, 2012
- International Business Machines Corporation
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Grant
LSSD compatibility for GSD unified global clock buffers
- Patent number 8,117,579
- Issue date Feb 14, 2012
- International Business Machines Corporation
- James Douglas Warnock
- G01 - MEASURING TESTING
Information Patent Grant
Integrated test waveform generator (TWG) and customer waveform gene...
- Patent number 7,996,807
- Issue date Aug 9, 2011
- International Business Machines Corporation
- Gary D. Grise
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Avoiding race conditions at clock domain crossings in an edge based...
- Patent number 7,996,739
- Issue date Aug 9, 2011
- International Business Machines Corporation
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Grant
Design structure and apparatus for a robust embedded interface
- Patent number 7,937,632
- Issue date May 3, 2011
- International Business Machines Corporation
- Steven M. Eustis
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for generating at-speed structural tests to impro...
- Patent number 7,856,607
- Issue date Dec 21, 2010
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus and method for selectively implementing launch off scan c...
- Patent number 7,721,170
- Issue date May 18, 2010
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
IC chip at-functional-speed testing with process coverage evaluation
- Patent number 7,620,921
- Issue date Nov 17, 2009
- International Business Machines Corporation
- Eric A. Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch and clock structures for enabling race-reduced MUX scan and L...
- Patent number 7,560,964
- Issue date Jul 14, 2009
- International Business Machines Corporation
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Grant
Testing of multiple asynchronous logic domains
- Patent number 7,529,294
- Issue date May 5, 2009
- International Business Machines Corporation
- Gary Douglas Grise
- G01 - MEASURING TESTING
Information Patent Grant
Microcontroller for logic built-in self test (LBIST)
- Patent number 7,490,280
- Issue date Feb 10, 2009
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
Design structure for monitoring cross chip delay variation on a sem...
- Patent number 7,487,487
- Issue date Feb 3, 2009
- International Business Machines Corporation
- Anthony D. Polson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch and clock structures for enabling race-reduced mux scan and L...
- Patent number 7,482,851
- Issue date Jan 27, 2009
- International Business Machines Corporation
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Grant
Negative edge flip-flops for muxscan and edge clock compatible LSSD
- Patent number 7,484,149
- Issue date Jan 27, 2009
- International Business Machines Corporation
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Grant
Arrangement for testing semiconductor chips while incorporated on a...
- Patent number 7,435,990
- Issue date Oct 14, 2008
- International Business Machines Corporation
- Brion L. Keller
- G01 - MEASURING TESTING
Information Patent Grant
Arrangement for testing semiconductor chips while incorporated on a...
- Patent number 7,381,986
- Issue date Jun 3, 2008
- International Business Machines Corporation
- Brion L. Keller
- G01 - MEASURING TESTING
Information Patent Grant
Nested voltage island architecture
- Patent number 7,131,074
- Issue date Oct 31, 2006
- International Business Machines Corporation
- Thomas R Bednar
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage island chip implementation
- Patent number 6,883,152
- Issue date Apr 19, 2005
- International Business Machines Corporation
- Thomas R. Bednar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for insertion of test points into integrated logic circuit d...
- Patent number 6,865,723
- Issue date Mar 8, 2005
- International Business Machines Corporation
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Grant
Pipeline array
- Patent number 6,856,270
- Issue date Feb 15, 2005
- International Business Machines Corporation
- Henry R. Farmer
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DISPOSITION OF INTEGRATED CIRCUITS USING PERFORMANCE SORT RING OSCI...
- Publication number 20130125076
- Publication date May 16, 2013
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TES...
- Publication number 20130125073
- Publication date May 16, 2013
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)
- Publication number 20120221910
- Publication date Aug 30, 2012
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Application
DENSE REGISTER ARRAY FOR ENABLING SCAN OUT OBSERVATION OF BOTH L1 A...
- Publication number 20120179944
- Publication date Jul 12, 2012
- International Business Machines Corporation
- Pamela S. Gillis
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGR...
- Publication number 20120124538
- Publication date May 17, 2012
- International Business Machines Corporation
- David E. LACKEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGR...
- Publication number 20120115256
- Publication date May 10, 2012
- International Business Machines Corporation
- David E. LACKEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGR...
- Publication number 20120112341
- Publication date May 10, 2012
- International Business Machines Corporation
- David E. LACKEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AVOIDING RACE CONDITIONS AT CLOCK DOMAIN CROSSINGS IN AN EDGE BASED...
- Publication number 20110066904
- Publication date Mar 17, 2011
- International Business Machines Corporation
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Application
Hold Transition Fault Model and Test Generation Method
- Publication number 20110055650
- Publication date Mar 3, 2011
- International Business Machines Corporation
- Vikram Iyengar
- G01 - MEASURING TESTING
Information Patent Application
STRUCTURE AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE
- Publication number 20090319841
- Publication date Dec 24, 2009
- Steven M. Eustis
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE
- Publication number 20090319818
- Publication date Dec 24, 2009
- Steven M. Eustis
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED TEST WAVEFORM GENERATOR (TWG) AND CUSTOMER WAVEFORM GENE...
- Publication number 20090265677
- Publication date Oct 22, 2009
- Gary D. Grise
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LSSD compatibility for GSD unified global clock buffers
- Publication number 20090199036
- Publication date Aug 6, 2009
- James D. Warnock
- G01 - MEASURING TESTING
Information Patent Application
CRITICAL PATH SELECTION FOR AT-SPEED TEST
- Publication number 20090150844
- Publication date Jun 11, 2009
- International Business Machines Corporation
- Vikram Iyengar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR GENERATING AT-SPEED STRUCTURAL TESTS TO IMPRO...
- Publication number 20090119629
- Publication date May 7, 2009
- Gary D. Grise
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR SELECTIVELY IMPLEMENTING LAUNCH OFF SCAN C...
- Publication number 20090106608
- Publication date Apr 23, 2009
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGR...
- Publication number 20090094565
- Publication date Apr 9, 2009
- David E. Lackey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)
- Publication number 20090055696
- Publication date Feb 26, 2009
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Application
NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD
- Publication number 20080270861
- Publication date Oct 30, 2008
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Application
IC CHIP AT-FUNCTIONAL-SPEED TESTING WITH PROCESS COVERAGE EVALUATION
- Publication number 20080270953
- Publication date Oct 30, 2008
- Eric A. Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS OF SYNCHRONOUS DIGITAL OPERATION AND SCAN BASED TESTING OF...
- Publication number 20080270863
- Publication date Oct 30, 2008
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Application
LATCH AND CLOCK STRUCTURES FOR ENABLING RACE-REDUCED MUX SCAN AND L...
- Publication number 20080042712
- Publication date Feb 21, 2008
- International Business Machines Corporation
- David E. LACKEY
- G01 - MEASURING TESTING
Information Patent Application
NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD
- Publication number 20070220382
- Publication date Sep 20, 2007
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Application
TESTING OF MULTIPLE ASYNCHRONOUS LOGIC DOMAINS
- Publication number 20070204194
- Publication date Aug 30, 2007
- Gary Douglas Grise
- G01 - MEASURING TESTING
Information Patent Application
MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)
- Publication number 20070204193
- Publication date Aug 30, 2007
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Application
Arrangement for testing semiconductor chips while incorporated on a...
- Publication number 20060284174
- Publication date Dec 21, 2006
- Brion L. Keller
- G01 - MEASURING TESTING
Information Patent Application
Latch and clock structures for enabling race-reduced MUX scan and L...
- Publication number 20060208783
- Publication date Sep 21, 2006
- IBM Corporation (International Business Machines)
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Application
NESTED VOLTAGE ISLAND ARCHITECTURE
- Publication number 20050010887
- Publication date Jan 13, 2005
- International Business Machines Corporation
- Thomas R. Bednar
- G11 - INFORMATION STORAGE
Information Patent Application
Voltage island chip implementation
- Publication number 20040243958
- Publication date Dec 2, 2004
- Thomas R. Bednar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AN ARRANGEMENT FOR TESTING SEMICONDUCTOR CHIPS WHILE INCORPORATED O...
- Publication number 20040135231
- Publication date Jul 15, 2004
- International Business Machines Corporation
- Brion L. Keller
- G01 - MEASURING TESTING

David E. Lackey

Person

Patents Grantslast 30 patents

Method and device for selectively adding timing margin in an integr...

Test path selection and test program generation for performance tes...

Method and device for selectively adding timing margin in an integr...

Method and device for selectively adding timing margin in an integr...

Disposition of integrated circuits using performance sort ring osci...

Dense register array for enabling scan out observation of both L1 a...

Microcontroller for logic built-in self test (LBIST)

Method and apparatus for a robust embedded interface

Microcontroller for logic built-in self test (LBIST)

Hold transition fault model and test generation method

Method and device for selectively adding timing margin in an integr...

LSSD compatibility for GSD unified global clock buffers

Integrated test waveform generator (TWG) and customer waveform gene...

Avoiding race conditions at clock domain crossings in an edge based...

Design structure and apparatus for a robust embedded interface

System and method for generating at-speed structural tests to impro...

Apparatus and method for selectively implementing launch off scan c...

IC chip at-functional-speed testing with process coverage evaluation

Latch and clock structures for enabling race-reduced MUX scan and L...

Testing of multiple asynchronous logic domains

Microcontroller for logic built-in self test (LBIST)

Design structure for monitoring cross chip delay variation on a sem...

Latch and clock structures for enabling race-reduced mux scan and L...

Negative edge flip-flops for muxscan and edge clock compatible LSSD

Arrangement for testing semiconductor chips while incorporated on a...

Arrangement for testing semiconductor chips while incorporated on a...

Nested voltage island architecture

Voltage island chip implementation

Method for insertion of test points into integrated logic circuit d...

Pipeline array

Patents Applicationslast 30 patents

DISPOSITION OF INTEGRATED CIRCUITS USING PERFORMANCE SORT RING OSCI...

TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TES...

MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)

DENSE REGISTER ARRAY FOR ENABLING SCAN OUT OBSERVATION OF BOTH L1 A...

METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGR...

METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGR...

METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGR...

AVOIDING RACE CONDITIONS AT CLOCK DOMAIN CROSSINGS IN AN EDGE BASED...

Hold Transition Fault Model and Test Generation Method

STRUCTURE AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE

METHOD AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE

INTEGRATED TEST WAVEFORM GENERATOR (TWG) AND CUSTOMER WAVEFORM GENE...

LSSD compatibility for GSD unified global clock buffers

CRITICAL PATH SELECTION FOR AT-SPEED TEST

SYSTEM AND METHOD FOR GENERATING AT-SPEED STRUCTURAL TESTS TO IMPRO...

APPARATUS AND METHOD FOR SELECTIVELY IMPLEMENTING LAUNCH OFF SCAN C...

METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGR...

MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)

NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD

IC CHIP AT-FUNCTIONAL-SPEED TESTING WITH PROCESS COVERAGE EVALUATION

METHODS OF SYNCHRONOUS DIGITAL OPERATION AND SCAN BASED TESTING OF...

LATCH AND CLOCK STRUCTURES FOR ENABLING RACE-REDUCED MUX SCAN AND L...

NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD

TESTING OF MULTIPLE ASYNCHRONOUS LOGIC DOMAINS

MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)

Arrangement for testing semiconductor chips while incorporated on a...

Latch and clock structures for enabling race-reduced MUX scan and L...

NESTED VOLTAGE ISLAND ARCHITECTURE

Voltage island chip implementation

AN ARRANGEMENT FOR TESTING SEMICONDUCTOR CHIPS WHILE INCORPORATED O...