David E. Richter

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Shared register architecture for a dual-instruction-set CPU to faci...
- Patent number 6,076,155
- Issue date Jun 13, 2000
- S3 Incorporated
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug and video queue for multi-processor chip
- Patent number 5,848,264
- Issue date Dec 8, 1998
- S3 Incorporated
- Brian R. Baird
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-instruction-set CPU having shared register for storing data be...
- Patent number 5,805,918
- Issue date Sep 8, 1998
- S3 Incorporated
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Merge/mask, rotate/shift, and boolean operations from two instructi...
- Patent number 5,781,457
- Issue date Jul 14, 1998
- Exponential Technology, Inc.
- Earl T. Cohen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-instruction-set architecture CPU with hidden software emulatio...
- Patent number 5,781,750
- Issue date Jul 14, 1998
- Exponential Technology, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared floating-point registers and register port-pairing in a dual...
- Patent number 5,685,009
- Issue date Nov 4, 1997
- Exponential Technology, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for emulating multiple debug breakpoints by page partitionin...
- Patent number 5,664,159
- Issue date Sep 2, 1997
- Exponential Technology, Inc.
- David E. Richter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translator having segment bounds encoding for storage in a TLB
- Patent number 5,652,872
- Issue date Jul 29, 1997
- Exponential Technology, Inc.
- David E. Richter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Program watchpoint checking using paging with sub-page validity
- Patent number 5,598,553
- Issue date Jan 28, 1997
- Exponential Technology, Inc.
- David E. Richter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Emulating operating system calls in an alternate instruction set us...
- Patent number 5,481,684
- Issue date Jan 2, 1996
- Exponential Technology, Inc.
- David E. Richter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared register architecture for a dual-instruction-set CPU
- Patent number 5,481,693
- Issue date Jan 2, 1996
- Exponential Technology, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor with operation capture facility
- Patent number 5,455,909
- Issue date Oct 3, 1995
- Chips and Technologies Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Emulation of segment bounds checking using paging with sub-page val...
- Patent number 5,440,710
- Issue date Aug 8, 1995
- Exponential Technology, Inc.
- David E. Richter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor with OEM mode for power management with input/output...
- Patent number 5,274,791
- Issue date Dec 28, 1993
- Chips & Technologies, Inc.
- Jimmy E. Bracking
- G06 - COMPUTING CALCULATING COUNTING

David E. Richter

Person

Patents Grantslast 30 patents

Shared register architecture for a dual-instruction-set CPU to faci...

Debug and video queue for multi-processor chip

Dual-instruction-set CPU having shared register for storing data be...

Merge/mask, rotate/shift, and boolean operations from two instructi...

Dual-instruction-set architecture CPU with hidden software emulatio...

Shared floating-point registers and register port-pairing in a dual...

Method for emulating multiple debug breakpoints by page partitionin...

Translator having segment bounds encoding for storage in a TLB

Program watchpoint checking using paging with sub-page validity

Emulating operating system calls in an alternate instruction set us...

Shared register architecture for a dual-instruction-set CPU

Microprocessor with operation capture facility

Emulation of segment bounds checking using paging with sub-page val...

Microprocessor with OEM mode for power management with input/output...