David Edward Fisch

Person

Pleasanton, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Transistor level interconnection methodologies utilizing 3D interco...
- Patent number 12,272,730
- Issue date Apr 8, 2025
- Adeia Semiconductor Inc.
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile dynamic random access memory
- Patent number 12,113,054
- Issue date Oct 8, 2024
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Direct-bonded native interconnects and active base die
- Patent number 11,823,906
- Issue date Nov 21, 2023
- Xcelsis Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor level interconnection methodologies utilizing 3D interco...
- Patent number 11,688,776
- Issue date Jun 27, 2023
- Adeia Semiconductor Inc.
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D memory circuit
- Patent number 11,599,299
- Issue date Mar 7, 2023
- Invensas LLC
- Javier A. DeLaCruz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-die module with low power operation
- Patent number 11,398,258
- Issue date Jul 26, 2022
- Invensas LLC
- David Edward Fisch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Direct-bonded native interconnects and active base die
- Patent number 11,289,333
- Issue date Mar 29, 2022
- Xcelsis Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Back biasing of FD-SOI circuit blocks
- Patent number 11,127,738
- Issue date Sep 21, 2021
- Xcelsis Corporation
- Javier A. Delacruz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Transistor level interconnection methodologies utilizing 3D interco...
- Patent number 10,991,804
- Issue date Apr 27, 2021
- Xcelsis Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Direct-bonded native interconnects and active base die
- Patent number 10,832,912
- Issue date Nov 10, 2020
- Xcelsis Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self healing compute array
- Patent number 10,684,929
- Issue date Jun 16, 2020
- Xcelsis Corporation
- Javier A. Delacruz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Direct-bonded native interconnects and active base die
- Patent number 10,522,352
- Issue date Dec 31, 2019
- Xcelsis Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DRAM adjacent row disturb mitigation
- Patent number 10,262,717
- Issue date Apr 16, 2019
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Grant
On-chip impedance network with digital coarse and analog fine tuning
- Patent number 10,164,633
- Issue date Dec 25, 2018
- Invensas Corporation
- Curtis Dicke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
DRAM adjacent row disturb mitigation
- Patent number 9,812,185
- Issue date Nov 7, 2017
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Grant
On-chip impedance network with digital coarse and analog fine tuning
- Patent number 9,705,497
- Issue date Jul 11, 2017
- Invensas Corporation
- Curtis Dicke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Packaged microelectronic elements having blind vias for heat dissip...
- Patent number 9,620,433
- Issue date Apr 11, 2017
- Tessera, Inc.
- David Edward Fisch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Retention optimized memory device using predictive data inversion
- Patent number 9,548,101
- Issue date Jan 17, 2017
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Grant
Retention optimized memory device using predictive data inversion
- Patent number 9,299,398
- Issue date Mar 29, 2016
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory devices having vertical drain to gate capacitiv...
- Patent number 9,230,814
- Issue date Jan 5, 2016
- Invensas Corporation
- David Edward Fisch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic elements with master/slave configurability
- Patent number 9,153,533
- Issue date Oct 6, 2015
- Invensas Corporation
- Belgacem Haba
- G11 - INFORMATION STORAGE
Information Patent Grant
On-chip impedance network with digital coarse and analog fine tuning
- Patent number 9,111,671
- Issue date Aug 18, 2015
- Invensas Corporation
- Curtis Dicke
- G11 - INFORMATION STORAGE
Information Patent Grant
Retention optimized memory device using predictive data inversion
- Patent number 9,007,866
- Issue date Apr 14, 2015
- Tessera Inc.
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Grant
Common doped region with separate gate control for a logic compatib...
- Patent number 8,873,302
- Issue date Oct 28, 2014
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Grant
Packaged microelectronic elements having blind vias for heat dissip...
- Patent number 8,618,647
- Issue date Dec 31, 2013
- Tessera, Inc.
- David Edward Fisch
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
NON-VOLATILE DYNAMIC RANDOM ACCESS MEMORY
- Publication number 20250038162
- Publication date Jan 30, 2025
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Direct-Bonded Native Interconnects And Active Base Die
- Publication number 20240265305
- Publication date Aug 8, 2024
- Adeia Semiconductor Inc.
- Javier A. DeLaCruz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D MEMORY CIRCUIT
- Publication number 20230376234
- Publication date Nov 23, 2023
- Invensas LLC
- Javier A. DeLaCruz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSISTOR LEVEL INTERCONNECTION METHODOLOGIES UTILIZING 3D INTERCO...
- Publication number 20230138732
- Publication date May 4, 2023
- Adeia Semiconductor Inc.
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Direct-Bonded Native Interconnects And Active Base Die
- Publication number 20220238339
- Publication date Jul 28, 2022
- Xcelsis Corporation
- Javier A. DELACRUZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Back Biasing of FD-SOI Circuit Block
- Publication number 20220020741
- Publication date Jan 20, 2022
- Xcelsis Corporation
- Javier A. DELACRUZ
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES FOR MANUFACTURING SPLIT-CELL 3D-NAND MEMORY DEVICES
- Publication number 20220005827
- Publication date Jan 6, 2022
- Invensas Corporation
- Xu Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Transistor Level Interconnection Methodologies Utilizing 3D Interco...
- Publication number 20210217858
- Publication date Jul 15, 2021
- Xcelsis Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D MEMORY CIRCUIT
- Publication number 20210149586
- Publication date May 20, 2021
- Invensas Corporation
- Javier A. DeLaCruz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Non-Volatile Dynamic Random Access Memory
- Publication number 20210118864
- Publication date Apr 22, 2021
- Invensas Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Direct-Bonded Native Interconnects And Active Base Die
- Publication number 20200357641
- Publication date Nov 12, 2020
- Xcelsis Corporation
- Javier A. DELACRUZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIRECT-BONDED NATIVE INTERCONNECTS AND ACTIVE BASE DIE
- Publication number 20200194262
- Publication date Jun 18, 2020
- Xcelsis Corporation
- Javier A. DELACRUZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Eliminating defects in stacks
- Publication number 20190393204
- Publication date Dec 26, 2019
- Xcelsis Corporation
- Javier A. DELACRUZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-DIE MODULE WITH LOW POWER OPERATION
- Publication number 20190333550
- Publication date Oct 31, 2019
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Application
Transistor Level Interconnection Methodologies Utilizing 3d Interco...
- Publication number 20190305093
- Publication date Oct 3, 2019
- Xcelsis Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Back biasing of FD-SOI circuit blocks
- Publication number 20190252375
- Publication date Aug 15, 2019
- Xcelsis Corporation
- Javier A. DELACRUZ
- G11 - INFORMATION STORAGE
Information Patent Application
Self Healing Compute Array
- Publication number 20180173600
- Publication date Jun 21, 2018
- Invensas Corporation
- Javier A. DELACRUZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM Adjacent Row Disturb Mitigation
- Publication number 20180114561
- Publication date Apr 26, 2018
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Application
Direct-bonded native interconnects and active base die
- Publication number 20180102251
- Publication date Apr 12, 2018
- INVENSAS BONDING TECHNOLOGIES, INC.
- Javier A. DELACRUZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
On-Chip Impedance Network with Digital Coarse and Analog Fine Tuning
- Publication number 20170310322
- Publication date Oct 26, 2017
- Invensas Corporation
- Curtis Dicke
- G11 - INFORMATION STORAGE
Information Patent Application
Packaged microelectronic elements having blind vias for heat dissip...
- Publication number 20170207141
- Publication date Jul 20, 2017
- Tessera, Inc.
- David Edward Fisch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRAM Adjacent Row Disturb Mitigation
- Publication number 20170117030
- Publication date Apr 27, 2017
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Application
Retention optimized memory device using predictive data inversion
- Publication number 20160189765
- Publication date Jun 30, 2016
- Invensas Corporation
- David Edward FISCH
- G11 - INFORMATION STORAGE
Information Patent Application
ON-CHIP IMPEDANCE NETWORK WITH DIGITAL COARSE AND ANALOG FINE TUNING
- Publication number 20160094223
- Publication date Mar 31, 2016
- Curtis DICKE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Retention optimized memory device using predictive data inversion
- Publication number 20150213847
- Publication date Jul 30, 2015
- Invensas Corporation
- David Edward FISCH
- G11 - INFORMATION STORAGE
Information Patent Application
RETENTION OPTIMIZED MEMORY DEVICE USING PREDICTIVE DATA INVERSION
- Publication number 20140313834
- Publication date Oct 23, 2014
- Invensas Corporation
- David Edward FISCH
- G11 - INFORMATION STORAGE
Information Patent Application
MICROELECTRONIC ELEMENTS WITH MASTER/SLAVE CONFIGURABILITY
- Publication number 20140264730
- Publication date Sep 18, 2014
- Invensas Corporation
- Belgacem Haba
- G11 - INFORMATION STORAGE
Information Patent Application
PACKAGED MICROELECTRONIC ELEMENTS HAVING BLIND VIAS FOR HEAT DISSIP...
- Publication number 20140175647
- Publication date Jun 26, 2014
- Tessera. Inc.
- David Edward Fisch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ON-CHIP IMPEDANCE NETWORK WITH DIGITAL COARSE AND ANALOG FINE TUNING
- Publication number 20140049356
- Publication date Feb 20, 2014
- Curtis DICKE
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY DEVICES HAVING VERTICAL DRAIN TO GATE CAPACITIV...
- Publication number 20130107630
- Publication date May 2, 2013
- Invensas Corporation
- David Edward Fisch
- H01 - BASIC ELECTRIC ELEMENTS

David Edward Fisch

Person

Patents Grantslast 30 patents

Transistor level interconnection methodologies utilizing 3D interco...

Non-volatile dynamic random access memory

Direct-bonded native interconnects and active base die

Transistor level interconnection methodologies utilizing 3D interco...

3D memory circuit

Multi-die module with low power operation

Direct-bonded native interconnects and active base die

Back biasing of FD-SOI circuit blocks

Transistor level interconnection methodologies utilizing 3D interco...

Direct-bonded native interconnects and active base die

Self healing compute array

Direct-bonded native interconnects and active base die

DRAM adjacent row disturb mitigation

On-chip impedance network with digital coarse and analog fine tuning

DRAM adjacent row disturb mitigation

On-chip impedance network with digital coarse and analog fine tuning

Packaged microelectronic elements having blind vias for heat dissip...

Retention optimized memory device using predictive data inversion

Retention optimized memory device using predictive data inversion

Non-volatile memory devices having vertical drain to gate capacitiv...

Microelectronic elements with master/slave configurability

On-chip impedance network with digital coarse and analog fine tuning

Retention optimized memory device using predictive data inversion

Common doped region with separate gate control for a logic compatib...

Packaged microelectronic elements having blind vias for heat dissip...

Patents Applicationslast 30 patents

NON-VOLATILE DYNAMIC RANDOM ACCESS MEMORY

Direct-Bonded Native Interconnects And Active Base Die

3D MEMORY CIRCUIT

TRANSISTOR LEVEL INTERCONNECTION METHODOLOGIES UTILIZING 3D INTERCO...

Direct-Bonded Native Interconnects And Active Base Die

Back Biasing of FD-SOI Circuit Block

TECHNIQUES FOR MANUFACTURING SPLIT-CELL 3D-NAND MEMORY DEVICES

Transistor Level Interconnection Methodologies Utilizing 3D Interco...

3D MEMORY CIRCUIT

Non-Volatile Dynamic Random Access Memory

Direct-Bonded Native Interconnects And Active Base Die

DIRECT-BONDED NATIVE INTERCONNECTS AND ACTIVE BASE DIE

Eliminating defects in stacks

MULTI-DIE MODULE WITH LOW POWER OPERATION

Transistor Level Interconnection Methodologies Utilizing 3d Interco...

Back biasing of FD-SOI circuit blocks

Self Healing Compute Array

DRAM Adjacent Row Disturb Mitigation

Direct-bonded native interconnects and active base die

On-Chip Impedance Network with Digital Coarse and Analog Fine Tuning

Packaged microelectronic elements having blind vias for heat dissip...

DRAM Adjacent Row Disturb Mitigation

Retention optimized memory device using predictive data inversion

ON-CHIP IMPEDANCE NETWORK WITH DIGITAL COARSE AND ANALOG FINE TUNING

Retention optimized memory device using predictive data inversion

RETENTION OPTIMIZED MEMORY DEVICE USING PREDICTIVE DATA INVERSION

MICROELECTRONIC ELEMENTS WITH MASTER/SLAVE CONFIGURABILITY

PACKAGED MICROELECTRONIC ELEMENTS HAVING BLIND VIAS FOR HEAT DISSIP...

ON-CHIP IMPEDANCE NETWORK WITH DIGITAL COARSE AND ANALOG FINE TUNING

NON-VOLATILE MEMORY DEVICES HAVING VERTICAL DRAIN TO GATE CAPACITIV...