David Hely

Person

Chemin Vallon de Toulouse, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Method and device for detecting an erroneous jump during program ex...
- Patent number 8,495,734
- Issue date Jul 23, 2013
- STMicroelectronics S.A.
- Frédéric Bancel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic circuit comprising a test mode secured by insertion of d...
- Patent number 7,930,605
- Issue date Apr 19, 2011
- STMicroelectronics S.A.
- Frederic Bancel
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit comprising a test mode secured by the use of an...
- Patent number 7,921,342
- Issue date Apr 5, 2011
- STMicroelectronics S.A.
- Frederic Bancel
- G01 - MEASURING TESTING
Information Patent Grant
Detection of a disturbance in the state of an electronic circuit fl...
- Patent number 7,768,318
- Issue date Aug 3, 2010
- STMicroelectronics (Rousset) SAS
- Frédéric Bancel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and device for securing the reading of a memory
- Patent number 7,747,935
- Issue date Jun 29, 2010
- STMicroelectronics S.A.
- Frédéric Bancel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Protecting an integrated circuit test mode
- Patent number 7,725,786
- Issue date May 25, 2010
- STMicroelectronics S.A.
- Frederic Bancel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit comprising a test mode secured by detection of t...
- Patent number 7,694,197
- Issue date Apr 6, 2010
- STMicroelectronics, S.A.
- Frédéric Bancel
- G01 - MEASURING TESTING
Information Patent Grant
Electronic circuit comprising a test mode secured by the breaking o...
- Patent number 7,676,717
- Issue date Mar 9, 2010
- STMicroelectronics S.A.
- Frederic Bancel
- G01 - MEASURING TESTING
Information Patent Grant
Method for testing an electronic circuit comprising a test mode sec...
- Patent number 7,577,886
- Issue date Aug 18, 2009
- STMicroelectronics, S.A.
- Frédéric Bancel
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit having configurable cells and a secured test mode
- Patent number 7,568,140
- Issue date Jul 28, 2009
- STMicroelectronics S.A.
- Frederic Bancel
- G01 - MEASURING TESTING
Information Patent Grant
Protecting an integrated circuit test mode
- Patent number 7,512,852
- Issue date Mar 31, 2009
- STMicroelectronics S.A.
- Frederic Bancel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Securing the test mode of an integrated circuit
- Patent number 7,484,152
- Issue date Jan 27, 2009
- STMicoelectronics SA
- Frederic Bancel
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of securing the test mode of an integrated circuit via intru...
- Patent number 7,478,293
- Issue date Jan 13, 2009
- STMicroelectronics S.A.
- Frederic Bancel
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit comprising a test mode secured by initialization...
- Patent number 7,308,635
- Issue date Dec 11, 2007
- STMicroelectronics S.A.
- Frederic Bancel
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DETECTION OF A DISTURBANCE IN THE STATE OF AN ELECTRONIC CIRCUIT FL...
- Publication number 20090315603
- Publication date Dec 24, 2009
- STMicroelectronics (Rousset) SAS
- Frederic Bancel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND DEVICE FOR DETECTING AN ERRONEOUS JUMP DURING PROGRAM EX...
- Publication number 20090254782
- Publication date Oct 8, 2009
- STMicroelectronics S.A.
- Frederic Bancel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROTECTING AN INTEGRATED CIRCUIT TEST MODE
- Publication number 20090164858
- Publication date Jun 25, 2009
- STMicroelectronics S.A.
- Frederic Bancel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND DEVICE FOR SECURING THE READING OF A MEMORY
- Publication number 20080228989
- Publication date Sep 18, 2008
- STMicroelectronics S.A.
- Frederic Bancel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Having Configurable Cells and a Secured Test Mode
- Publication number 20080191741
- Publication date Aug 14, 2008
- STMICROELECTRONICS AS
- Frederic Bancel
- G01 - MEASURING TESTING
Information Patent Application
ELECTRONIC CIRCUIT COMPRISING A TEST MODE SECURED BY INSERTION OF D...
- Publication number 20080022174
- Publication date Jan 24, 2008
- STMicroelectronics S.A.
- Frederic Bancel
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT COMPRISING A TEST MODE SECURED BY THE USE OF AN...
- Publication number 20070257701
- Publication date Nov 8, 2007
- STMicroelectronics S.A.
- Frederic Bancel
- G01 - MEASURING TESTING
Information Patent Application
ELECTRONIC CIRCUIT COMPRISING A TEST MODE SECURED BY THE BREAKING O...
- Publication number 20070234156
- Publication date Oct 4, 2007
- STMicroelectronics S.A.
- Frederic Bancel
- G01 - MEASURING TESTING
Information Patent Application
Method for testing an electronic circuit comprising a test mode sec...
- Publication number 20070043986
- Publication date Feb 22, 2007
- STMicroelectronics S.A.
- Frederic Bancel
- G01 - MEASURING TESTING
Information Patent Application
Integrated circuit comprising a test mode secured by detection of t...
- Publication number 20070033463
- Publication date Feb 8, 2007
- STMicroelectronics S.A.
- Frederic Bancel
- G01 - MEASURING TESTING
Information Patent Application
Securing the test mode of an integrated circuit
- Publication number 20060195723
- Publication date Aug 31, 2006
- STMicroelectronics S.A.
- Frederic Bancel
- G01 - MEASURING TESTING
Information Patent Application
Protecting an integrated circuit test mode
- Publication number 20050169076
- Publication date Aug 4, 2005
- Frederic Bancel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of securing the test mode of an integrated circuit via intru...
- Publication number 20050172184
- Publication date Aug 4, 2005
- Frederic Bancel
- G01 - MEASURING TESTING
Information Patent Application
Integrated circuit comprising a test mode secured by initialization...
- Publication number 20050172185
- Publication date Aug 4, 2005
- STMicroelectronics S.A.
- Frederic Bancel
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Method and device for detecting an erroneous jump during program ex...

Electronic circuit comprising a test mode secured by insertion of d...

Integrated circuit comprising a test mode secured by the use of an...

Detection of a disturbance in the state of an electronic circuit fl...

Method and device for securing the reading of a memory

Protecting an integrated circuit test mode

Integrated circuit comprising a test mode secured by detection of t...

Electronic circuit comprising a test mode secured by the breaking o...

Method for testing an electronic circuit comprising a test mode sec...

Integrated circuit having configurable cells and a secured test mode

Protecting an integrated circuit test mode

Securing the test mode of an integrated circuit

Method of securing the test mode of an integrated circuit via intru...

Integrated circuit comprising a test mode secured by initialization...

Patents Applicationslast 30 patents

DETECTION OF A DISTURBANCE IN THE STATE OF AN ELECTRONIC CIRCUIT FL...

METHOD AND DEVICE FOR DETECTING AN ERRONEOUS JUMP DURING PROGRAM EX...

PROTECTING AN INTEGRATED CIRCUIT TEST MODE

METHOD AND DEVICE FOR SECURING THE READING OF A MEMORY

Integrated Circuit Having Configurable Cells and a Secured Test Mode

ELECTRONIC CIRCUIT COMPRISING A TEST MODE SECURED BY INSERTION OF D...

INTEGRATED CIRCUIT COMPRISING A TEST MODE SECURED BY THE USE OF AN...

ELECTRONIC CIRCUIT COMPRISING A TEST MODE SECURED BY THE BREAKING O...

Method for testing an electronic circuit comprising a test mode sec...

Integrated circuit comprising a test mode secured by detection of t...

Securing the test mode of an integrated circuit

Protecting an integrated circuit test mode

Method of securing the test mode of an integrated circuit via intru...

Integrated circuit comprising a test mode secured by initialization...