David J. Sager

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Systems, apparatuses, and methods for a hardware and software syste...
- Patent number 10,725,755
- Issue date Jul 28, 2020
- Intel Corporation
- David J. Sager
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, apparatuses, and methods for a hardware and software syste...
- Patent number 9,672,019
- Issue date Jun 6, 2017
- Intel Corporation
- David J. Sager
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, apparatuses, and methods for a hardware and software syste...
- Patent number 9,189,233
- Issue date Nov 17, 2015
- Intel Corporation
- Ruchira Sasanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having execution core sections operating at different clo...
- Patent number RE45487
- Issue date Apr 21, 2015
- Intel Corporation
- David J. Sager
- 713 - Electrical computers and digital processing systems: support
Information Patent Grant
Tracking mechanism coupled to retirement in reorder buffer for indi...
- Patent number 8,914,617
- Issue date Dec 16, 2014
- Intel Corporation
- Shlomo Raikin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for assigning thread priority in a processor o...
- Patent number 8,850,165
- Issue date Sep 30, 2014
- Intel Corporation
- David W. Burns
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having execution core sections operating at different clo...
- Patent number RE44494
- Issue date Sep 10, 2013
- Intel Corporation
- David J. Sager
- 713 - Electrical computers and digital processing systems: support
Information Patent Grant
Replay instruction morphing
- Patent number 8,347,066
- Issue date Jan 1, 2013
- Intel Corporation
- Douglas M. Carmean
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for assigning thread priority in a processor o...
- Patent number 7,987,346
- Issue date Jul 26, 2011
- Intel Corporation
- David Burns
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for assigning thread priority in a processor o...
- Patent number 7,877,583
- Issue date Jan 25, 2011
- Intel Corporation
- David W. Burns
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for estimating and controlling di/dt-induced power supply...
- Patent number 7,742,910
- Issue date Jun 22, 2010
- Intel Corporation
- Edward T. Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for assigning thread priority in a processor o...
- Patent number 7,454,600
- Issue date Nov 18, 2008
- Intel Corporation
- David W. Burns
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fusing load and alu operations
- Patent number 7,398,372
- Issue date Jul 8, 2008
- Intel Corporation
- Nicholas G. Samra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for estimating and controlling di/dt-induced power supply...
- Patent number 7,236,920
- Issue date Jun 26, 2007
- Intel Corporation
- Edward T. Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-threading techniques for a processor utilizing a replay queue
- Patent number 7,219,349
- Issue date May 15, 2007
- Intel Corporation
- Amit A. Merchant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor with a replay system that includes a replay queue for imp...
- Patent number 7,200,737
- Issue date Apr 3, 2007
- Intel Corporation
- Amit A. Merchant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor and data cache with data storage unit and tag hit/miss lo...
- Patent number 7,100,012
- Issue date Aug 29, 2006
- Intel Corporation
- David J. Sager
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface to a memory system for a processor having a replay system
- Patent number 7,089,409
- Issue date Aug 8, 2006
- Intel Corporation
- Amit A. Merchant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for estimating and controlling di/dt-induced power supply...
- Patent number 7,035,785
- Issue date Apr 25, 2006
- Intel Corporation
- Edward T. Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Breaking replay dependency loops in a processor using a rescheduled...
- Patent number 6,981,129
- Issue date Dec 27, 2005
- Intel Corporation
- Darrell D. Boggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stopping replay tornadoes
- Patent number 6,952,764
- Issue date Oct 4, 2005
- Intel Corporation
- David J. Sager
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for controlling the processing priority betwee...
- Patent number 6,928,647
- Issue date Aug 9, 2005
- Intel Corporation
- David J. Sager
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speculative scheduling of instructions with source operand validity...
- Patent number 6,925,550
- Issue date Aug 2, 2005
- Intel Corporation
- Eric Sprangle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Replay instruction morphing
- Patent number 6,880,069
- Issue date Apr 12, 2005
- Intel Corporation
- Douglas M. Carmean
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for rescheduling multiple micro-operations in...
- Patent number 6,877,086
- Issue date Apr 5, 2005
- Intel Corporation
- Darrell D. Boggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storing of instructions relating to a stalled thread
- Patent number 6,792,446
- Issue date Sep 14, 2004
- Intel Corporation
- Amit A. Merchant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor including replay queue to break livelocks
- Patent number 6,785,803
- Issue date Aug 31, 2004
- Intel Corporation
- Amit A. Merchant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for address calculation
- Patent number 6,735,682
- Issue date May 11, 2004
- Intel Corporation
- Ross A. Segelken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having replay architecture with fast and slow replay paths
- Patent number 6,735,688
- Issue date May 11, 2004
- Intel Corporation
- Michael D. Upton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for executing computer instructions in parallel
- Patent number 6,704,861
- Issue date Mar 9, 2004
- Hewlett-Packard Development Company, L.P.
- Francis X. McKeen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTE...
- Publication number 20180060049
- Publication date Mar 1, 2018
- Intel Corporation
- DAVID J. SAGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRACKING CONTROL FLOW OF INSTRUCTIONS
- Publication number 20140281424
- Publication date Sep 18, 2014
- Jayaram Bobba
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTE...
- Publication number 20130166886
- Publication date Jun 27, 2013
- Ruchira Sasanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR HAVING EXECUTION CORE SECTIONS OPERATING AT DIFFERENT CLO...
- Publication number 20120042151
- Publication date Feb 16, 2012
- David J. Sager
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Assigning Thread Priority in a Processor o...
- Publication number 20110239221
- Publication date Sep 29, 2011
- David W. Burns
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MOVE ELIMINATION AND NEXT PAGE PREFETCHER
- Publication number 20110208918
- Publication date Aug 25, 2011
- Shlomo Raikin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTE...
- Publication number 20110167416
- Publication date Jul 7, 2011
- David J. Sager
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ASSIGNING THREAD PRIORITY IN A PROCESSOR O...
- Publication number 20110113222
- Publication date May 12, 2011
- Intel Corporation
- David W. BURNS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISMS TO HANDLE FREE PHYSICAL REGISTER IDENTIFIERS FOR SMT OUT...
- Publication number 20090327661
- Publication date Dec 31, 2009
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ASSIGNING THREAD PRIORITY IN A PROCESSOR O...
- Publication number 20090070562
- Publication date Mar 12, 2009
- Intel Corporation
- David W. BURNS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for estimating and controlling di/dt-induced power supply...
- Publication number 20070225959
- Publication date Sep 27, 2007
- Edward T. Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for estimating and controlling di/dt-induced power supply...
- Publication number 20060100840
- Publication date May 11, 2006
- Intel Corporation
- Edward T. Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Replay instruction morphing
- Publication number 20050172107
- Publication date Aug 4, 2005
- Douglas M. Carmean
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor having a RAT state history recovery mechanism
- Publication number 20040177239
- Publication date Sep 9, 2004
- David W. Clift
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-threading techniques for a processor utilizing a replay queue
- Publication number 20040172523
- Publication date Sep 2, 2004
- Amit A. Merchant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interface to a memory system for a processor having a replay system
- Publication number 20040083351
- Publication date Apr 29, 2004
- Amit A. Merchant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor and data cache with data storage unit and tag hit/miss lo...
- Publication number 20040019746
- Publication date Jan 29, 2004
- David J. Sager
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fusing load and alu operations
- Publication number 20030236966
- Publication date Dec 25, 2003
- Nicholas G. Samra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for address calculation
- Publication number 20030188125
- Publication date Oct 2, 2003
- Ross A. Segelken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for controlling the processing priority betwee...
- Publication number 20030158885
- Publication date Aug 21, 2003
- David J. Sager
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for controlling the processing priority betwee...
- Publication number 20030154235
- Publication date Aug 14, 2003
- David J. Sager
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for estimating and controlling di/dt-induced power supply...
- Publication number 20030125922
- Publication date Jul 3, 2003
- Edward T. Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to execute instructions in a processor
- Publication number 20030126417
- Publication date Jul 3, 2003
- Eric Sprangle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Stopping replay tornadoes
- Publication number 20030126405
- Publication date Jul 3, 2003
- David J. Sager
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for assigning thread priority in a processor o...
- Publication number 20020199088
- Publication date Dec 26, 2002
- David W. Burns
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-threading techniques for a processor utilizing a replay queue
- Publication number 20020091914
- Publication date Jul 11, 2002
- Amit A. Merchant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for partial merges for sub-register data operations
- Publication number 20020083307
- Publication date Jun 27, 2002
- David J. Sager
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor having execution core sections operating at different clo...
- Publication number 20010029590
- Publication date Oct 11, 2001
- Intel Corporation
- David J. Sager
- G06 - COMPUTING CALCULATING COUNTING

David J. Sager

Person

Patents Grantslast 30 patents

Systems, apparatuses, and methods for a hardware and software syste...

Systems, apparatuses, and methods for a hardware and software syste...

Systems, apparatuses, and methods for a hardware and software syste...

Processor having execution core sections operating at different clo...

Tracking mechanism coupled to retirement in reorder buffer for indi...

Method and apparatus for assigning thread priority in a processor o...

Processor having execution core sections operating at different clo...

Replay instruction morphing

Method and apparatus for assigning thread priority in a processor o...

Method and apparatus for assigning thread priority in a processor o...

Mechanism for estimating and controlling di/dt-induced power supply...

Method and apparatus for assigning thread priority in a processor o...

Fusing load and alu operations

Mechanism for estimating and controlling di/dt-induced power supply...

Multi-threading techniques for a processor utilizing a replay queue

Processor with a replay system that includes a replay queue for imp...

Processor and data cache with data storage unit and tag hit/miss lo...

Interface to a memory system for a processor having a replay system

Mechanism for estimating and controlling di/dt-induced power supply...

Breaking replay dependency loops in a processor using a rescheduled...

Stopping replay tornadoes

Method and apparatus for controlling the processing priority betwee...

Speculative scheduling of instructions with source operand validity...

Replay instruction morphing

Method and apparatus for rescheduling multiple micro-operations in...

Storing of instructions relating to a stalled thread

Processor including replay queue to break livelocks

Apparatus and method for address calculation

Processor having replay architecture with fast and slow replay paths

Mechanism for executing computer instructions in parallel

Patents Applicationslast 30 patents

SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTE...

TRACKING CONTROL FLOW OF INSTRUCTIONS

SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTE...

PROCESSOR HAVING EXECUTION CORE SECTIONS OPERATING AT DIFFERENT CLO...

Method and Apparatus for Assigning Thread Priority in a Processor o...

MOVE ELIMINATION AND NEXT PAGE PREFETCHER

SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTE...

METHOD AND APPARATUS FOR ASSIGNING THREAD PRIORITY IN A PROCESSOR O...

MECHANISMS TO HANDLE FREE PHYSICAL REGISTER IDENTIFIERS FOR SMT OUT...

METHOD AND APPARATUS FOR ASSIGNING THREAD PRIORITY IN A PROCESSOR O...

Mechanism for estimating and controlling di/dt-induced power supply...

Mechanism for estimating and controlling di/dt-induced power supply...

Replay instruction morphing

Processor having a RAT state history recovery mechanism

Multi-threading techniques for a processor utilizing a replay queue

Interface to a memory system for a processor having a replay system

Processor and data cache with data storage unit and tag hit/miss lo...

Fusing load and alu operations

Apparatus and method for address calculation

Method and apparatus for controlling the processing priority betwee...

Method and apparatus for controlling the processing priority betwee...

Mechanism for estimating and controlling di/dt-induced power supply...

Method and apparatus to execute instructions in a processor

Stopping replay tornadoes

Method and apparatus for assigning thread priority in a processor o...

Multi-threading techniques for a processor utilizing a replay queue

System and method for partial merges for sub-register data operations

Processor having execution core sections operating at different clo...