David J. Zimmerman

Person

El Dorado Hills, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Accelerated resource allocation techniques
- Patent number 11,507,430
- Issue date Nov 22, 2022
- Intel Corporation
- Rasika Subramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for accessing storage-as-memory
- Patent number 11,238,203
- Issue date Feb 1, 2022
- Intel Corporation
- Rameshkumar Illikkal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic partial power down of memory-side cache in a 2-level memory...
- Patent number 11,200,176
- Issue date Dec 14, 2021
- Intel Corporation
- Raj K Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic partial power down of memory-side cache in a 2-level memory...
- Patent number 10,795,823
- Issue date Oct 6, 2020
- Intel Corporation
- Raj K Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for implementing a multi-level memory hierarchy
- Patent number 10,719,443
- Issue date Jul 21, 2020
- Intel Corporation
- Raj K. Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write data mask for power reduction
- Patent number 10,541,009
- Issue date Jan 21, 2020
- Intel Corporation
- David J. Zimmerman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive configuration of non-volatile memory
- Patent number 10,504,591
- Issue date Dec 10, 2019
- Intel Corporation
- Shekoufeh Qawami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Boundary scan chain for stacked memory
- Patent number 10,347,354
- Issue date Jul 9, 2019
- Intel Corporation
- David J. Zimmerman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for implementing a multi-level memory hierarchy
- Patent number 10,241,912
- Issue date Mar 26, 2019
- Intel Corporation
- Raj K. Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-repair logic for stacked memory architecture
- Patent number 10,224,115
- Issue date Mar 5, 2019
- Intel Corporation
- Joon-Sung Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive configuration of non-volatile memory
- Patent number 10,026,475
- Issue date Jul 17, 2018
- Intel Corporation
- Shekoufeh Qawami
- G11 - INFORMATION STORAGE
Information Patent Grant
Interface for storage device access over memory bus
- Patent number 10,025,737
- Issue date Jul 17, 2018
- Intel Corporation
- Shekoufeh Qawami
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Integrated circuit defect detection and repair
- Patent number 9,922,725
- Issue date Mar 20, 2018
- Intel Corporation
- Bruce Querbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-repair logic for stacked memory architecture
- Patent number 9,646,720
- Issue date May 9, 2017
- Intel Corporation
- Joon-Sung Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for implementing a multi-level memory hierarchy
- Patent number 9,600,416
- Issue date Mar 21, 2017
- Intel Corporation
- Raj K. Ramanujan
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit defect detection and repair
- Patent number 9,564,245
- Issue date Feb 7, 2017
- Intel Corporation
- Bruce Querbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit defect detection and repair
- Patent number 9,548,137
- Issue date Jan 17, 2017
- Intel Corporation
- Bruce Querbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Boundary scan chain for stacked memory
- Patent number 9,476,940
- Issue date Oct 25, 2016
- Intel Corporation
- David J. Zimmerman
- G11 - INFORMATION STORAGE
Information Patent Grant
Bad block management mechanism
- Patent number 9,418,700
- Issue date Aug 16, 2016
- Intel Corporation
- Raj K. Ramanujan
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for implementing a multi-level memory hierarch...
- Patent number 9,317,429
- Issue date Apr 19, 2016
- Intel Corporation
- Raj K Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built-in self-test for stacked memory architecture
- Patent number 9,298,573
- Issue date Mar 29, 2016
- Intel Corporation
- Darshan Kobla
- G11 - INFORMATION STORAGE
Information Patent Grant
Generic address scrambler for memory circuit test engine
- Patent number 9,236,143
- Issue date Jan 12, 2016
- Intel Corporation
- Darshan Kobla
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive configuration of non-volatile memory
- Patent number 9,195,589
- Issue date Nov 24, 2015
- Intel Corporation
- Shekoufeh Qawami
- G11 - INFORMATION STORAGE
Information Patent Grant
Generic data scrambler for memory circuit test engine
- Patent number 9,190,173
- Issue date Nov 17, 2015
- Intel Corporation
- Darshan Kobla
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for error management in a memory device
- Patent number 9,158,616
- Issue date Oct 13, 2015
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On chip redundancy repair for memory devices
- Patent number 9,158,619
- Issue date Oct 13, 2015
- Intel Corporation
- Darshan Kobla
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-repair logic for stacked memory architecture
- Patent number 9,136,021
- Issue date Sep 15, 2015
- Intel Corporation
- Joon-Sung Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Input/output delay testing for devices utilizing on-chip delay gene...
- Patent number 9,110,134
- Issue date Aug 18, 2015
- Intel Corporation
- Tak M. Mak
- G01 - MEASURING TESTING
Information Patent Grant
Interface for storage device access over memory bus
- Patent number 9,064,560
- Issue date Jun 23, 2015
- Intel Corporation
- Shekoufeh Qawami
- G11 - INFORMATION STORAGE
Information Patent Grant
Low speed access to DRAM
- Patent number 9,036,718
- Issue date May 19, 2015
- Intel Corporation
- David J. Zimmerman
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DYNAMIC PARTIAL POWER DOWN OF MEMORY-SIDE CACHE IN A 2-LEVEL MEMORY...
- Publication number 20210056035
- Publication date Feb 25, 2021
- Intel Corporation
- Raj K. RAMANUJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATED RESOURCE ALLOCATION TECHNIQUES
- Publication number 20200104184
- Publication date Apr 2, 2020
- Rasika SUBRAMANIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY
- Publication number 20190220406
- Publication date Jul 18, 2019
- Intel Corporation
- Raj K. RAMANUJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE CONFIGURATION OF NON-VOLATILE MEMORY
- Publication number 20190057737
- Publication date Feb 21, 2019
- Intel Corporation
- Shekoufeh QAWAMI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE DATA MASK FOR POWER REDUCTION
- Publication number 20190035437
- Publication date Jan 31, 2019
- Intel Corporation
- DAVID J. ZIMMERMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR ACCESSING STORAGE-AS-MEMORY
- Publication number 20190005176
- Publication date Jan 3, 2019
- Intel Corporation
- Rameshkumar Illikkal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-REPAIR LOGIC FOR STACKED MEMORY ARCHITECTURE
- Publication number 20180005709
- Publication date Jan 4, 2018
- Intel Corporation
- Joon-Sung YANG
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY
- Publication number 20170249250
- Publication date Aug 31, 2017
- Intel Corporation
- Raj K. RAMANUJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOUNDARY SCAN CHAIN FOR STACKED MEMORY
- Publication number 20170169900
- Publication date Jun 15, 2017
- Intel Corporation
- David J. Zimmerman
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR
- Publication number 20170084351
- Publication date Mar 23, 2017
- Intel Corporation
- Bruce QUERBACH
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE CONFIGURATION OF NON-VOLATILE MEMORY
- Publication number 20160203864
- Publication date Jul 14, 2016
- Intel Corporation
- SHEKOUFEH QAWAMI
- G11 - INFORMATION STORAGE
Information Patent Application
SELF-REPAIR LOGIC FOR STACKED MEMORY ARCHITECTURE
- Publication number 20160055922
- Publication date Feb 25, 2016
- Intel Corporation
- Joon-Sung Yang
- G11 - INFORMATION STORAGE
Information Patent Application
INTERFACE FOR STORAGE DEVICE ACCESS OVER MEMORY BUS
- Publication number 20150269100
- Publication date Sep 24, 2015
- Shekoufeh Qawami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR
- Publication number 20150187436
- Publication date Jul 2, 2015
- Intel Corporation
- Bruce QUERBACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR
- Publication number 20150187439
- Publication date Jul 2, 2015
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING A WIDE FUNCTIONAL INTERFACE OF A DEVICE INTEGRATED ON AN SI...
- Publication number 20150187410
- Publication date Jul 2, 2015
- Christopher J Nelson
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC PARTIAL POWER DOWN OF MEMORY-SIDE CACHE IN A 2-LEVEL MEMO...
- Publication number 20140304475
- Publication date Oct 9, 2014
- Raj K Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERIC ADDRESS SCRAMBLER FOR MEMORY CIRCUIT TEST ENGINE
- Publication number 20140237307
- Publication date Aug 21, 2014
- Darshan Kobla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INPUT/OUTPUT DELAY TESTING FOR DEVICES UTILIZING ON-CHIP DELAY GENE...
- Publication number 20140189457
- Publication date Jul 3, 2014
- Tak M. Mak
- G01 - MEASURING TESTING
Information Patent Application
BUILT-IN SELF-TEST FOR STACKED MEMORY ARCHITECTURE
- Publication number 20140164833
- Publication date Jun 12, 2014
- Darshan Kobla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY
- Publication number 20140129767
- Publication date May 8, 2014
- Raj K Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOUNDARY SCAN CHAIN FOR STACKED MEMORY
- Publication number 20140122952
- Publication date May 1, 2014
- David J. Zimmerman
- G01 - MEASURING TESTING
Information Patent Application
LOW SPEED ACCESS TO DRAM
- Publication number 20140108696
- Publication date Apr 17, 2014
- David J. Zimmerman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM AND APPARATUS FOR EVALUATION OF INPUT/OUTPUT BUFFER...
- Publication number 20140089752
- Publication date Mar 27, 2014
- Christopher J. Nelson
- G01 - MEASURING TESTING
Information Patent Application
INTERFACE FOR STORAGE DEVICE ACCESS OVER MEMORY BUS
- Publication number 20140075107
- Publication date Mar 13, 2014
- Shekoufeh Qawami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON CHIP REDUNDANCY REPAIR FOR MEMORY DEVICES
- Publication number 20140013185
- Publication date Jan 9, 2014
- Darshan Kobla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERIC ADDRESS SCRAMBLER FOR MEMORY CIRCUIT TEST ENGINE
- Publication number 20140013169
- Publication date Jan 9, 2014
- Darshan Kobla
- G11 - INFORMATION STORAGE
Information Patent Application
BAD BLOCK MANAGEMENT MECHANISM
- Publication number 20140006848
- Publication date Jan 2, 2014
- RAJ K. RAMANUJAN
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE CONFIGURATION OF NON-VOLATILE MEMORY
- Publication number 20130339589
- Publication date Dec 19, 2013
- Shekoufeh Qawami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-REPAIR LOGIC FOR STACKED MEMORY ARCHITECTURE
- Publication number 20130294184
- Publication date Nov 7, 2013
- Joon-Sung Yang
- G11 - INFORMATION STORAGE

David J. Zimmerman

Person

Patents Grantslast 30 patents

Accelerated resource allocation techniques

Systems and methods for accessing storage-as-memory

Dynamic partial power down of memory-side cache in a 2-level memory...

Dynamic partial power down of memory-side cache in a 2-level memory...

Apparatus and method for implementing a multi-level memory hierarchy

Write data mask for power reduction

Adaptive configuration of non-volatile memory

Boundary scan chain for stacked memory

Apparatus and method for implementing a multi-level memory hierarchy

Self-repair logic for stacked memory architecture

Adaptive configuration of non-volatile memory

Interface for storage device access over memory bus

Integrated circuit defect detection and repair

Self-repair logic for stacked memory architecture

Apparatus and method for implementing a multi-level memory hierarchy

Integrated circuit defect detection and repair

Integrated circuit defect detection and repair

Boundary scan chain for stacked memory

Bad block management mechanism

Apparatus and method for implementing a multi-level memory hierarch...

Built-in self-test for stacked memory architecture

Generic address scrambler for memory circuit test engine

Adaptive configuration of non-volatile memory

Generic data scrambler for memory circuit test engine

Method and system for error management in a memory device

On chip redundancy repair for memory devices

Self-repair logic for stacked memory architecture

Input/output delay testing for devices utilizing on-chip delay gene...

Interface for storage device access over memory bus

Low speed access to DRAM

Patents Applicationslast 30 patents

DYNAMIC PARTIAL POWER DOWN OF MEMORY-SIDE CACHE IN A 2-LEVEL MEMORY...

ACCELERATED RESOURCE ALLOCATION TECHNIQUES

APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY

ADAPTIVE CONFIGURATION OF NON-VOLATILE MEMORY

WRITE DATA MASK FOR POWER REDUCTION

SYSTEMS AND METHODS FOR ACCESSING STORAGE-AS-MEMORY

SELF-REPAIR LOGIC FOR STACKED MEMORY ARCHITECTURE

APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY

BOUNDARY SCAN CHAIN FOR STACKED MEMORY

INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR

ADAPTIVE CONFIGURATION OF NON-VOLATILE MEMORY

SELF-REPAIR LOGIC FOR STACKED MEMORY ARCHITECTURE

INTERFACE FOR STORAGE DEVICE ACCESS OVER MEMORY BUS

INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR

INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR

TESTING A WIDE FUNCTIONAL INTERFACE OF A DEVICE INTEGRATED ON AN SI...

DYNAMIC PARTIAL POWER DOWN OF MEMORY-SIDE CACHE IN A 2-LEVEL MEMO...

GENERIC ADDRESS SCRAMBLER FOR MEMORY CIRCUIT TEST ENGINE

INPUT/OUTPUT DELAY TESTING FOR DEVICES UTILIZING ON-CHIP DELAY GENE...

BUILT-IN SELF-TEST FOR STACKED MEMORY ARCHITECTURE

APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY

BOUNDARY SCAN CHAIN FOR STACKED MEMORY

LOW SPEED ACCESS TO DRAM

METHOD, SYSTEM AND APPARATUS FOR EVALUATION OF INPUT/OUTPUT BUFFER...

INTERFACE FOR STORAGE DEVICE ACCESS OVER MEMORY BUS

ON CHIP REDUNDANCY REPAIR FOR MEMORY DEVICES

GENERIC ADDRESS SCRAMBLER FOR MEMORY CIRCUIT TEST ENGINE

BAD BLOCK MANAGEMENT MECHANISM

ADAPTIVE CONFIGURATION OF NON-VOLATILE MEMORY

SELF-REPAIR LOGIC FOR STACKED MEMORY ARCHITECTURE