David Lewis

Person

Toronto, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for performing symbolic timing analysis with s...
- Patent number 10,311,196
- Issue date Jun 4, 2019
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Regional design-dependent voltage control and clocking
- Patent number 10,303,834
- Issue date May 28, 2019
- Intel Corporation
- David Michael Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Omnibus logic element
- Patent number 10,177,766
- Issue date Jan 8, 2019
- Altera Corporation
- James Schleicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined interconnect circuitry with double data rate interconnect...
- Patent number 10,141,936
- Issue date Nov 27, 2018
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Regional design-dependent voltage control and clocking
- Patent number 10,055,526
- Issue date Aug 21, 2018
- Intel Corporation
- David Michael Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit device configuration methods adapted to account...
- Patent number 10,037,396
- Issue date Jul 31, 2018
- Altera Corporation
- Ryan Fung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Routing and programming for resistive switch arrays
- Patent number 10,027,327
- Issue date Jul 17, 2018
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tristate multiplexers with immunity to aging effects
- Patent number 9,941,882
- Issue date Apr 10, 2018
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for bypassing defects in rows of circuits
- Patent number 9,893,732
- Issue date Feb 13, 2018
- Intel Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable storage blocks with embedded first-in first-out and de...
- Patent number 9,824,024
- Issue date Nov 21, 2017
- Altera Corporation
- Carl Ebeling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry for implementing multi-mode redundancy and arithmetic fun...
- Patent number 9,813,061
- Issue date Nov 7, 2017
- Altera Corporation
- Herman Henry Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Metastability-hardened synchronization circuit
- Patent number 9,697,309
- Issue date Jul 4, 2017
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined interconnect circuitry with double data rate interconnect...
- Patent number 9,692,418
- Issue date Jun 27, 2017
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuits with improved register circuitry
- Patent number 9,660,650
- Issue date May 23, 2017
- Altera Corporation
- Valavan Manohararajah
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Structures for LUT-based arithmetic in PLDs
- Patent number 9,658,830
- Issue date May 23, 2017
- Altera Corporation
- Ketan Padalia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Error detection and correction circuitry
- Patent number 9,600,366
- Issue date Mar 21, 2017
- Altera Corporation
- Paul B. Ekas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for detecting memory bit corruption on an int...
- Patent number 9,582,349
- Issue date Feb 28, 2017
- Altera Corporation
- Herman Henry Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuring programmable integrated circuit device resources as pro...
- Patent number 9,553,590
- Issue date Jan 24, 2017
- Altera Corporation
- Valavan Manohararajah
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
First-in-first-out memory with dual memory banks
- Patent number 9,501,407
- Issue date Nov 22, 2016
- Altera Corporation
- Ray Ruey-Hsien Hu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Omnibus logic element
- Patent number 9,496,875
- Issue date Nov 15, 2016
- Altera Corporation
- James Schleicher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Transition accelerator circuitry
- Patent number 9,479,173
- Issue date Oct 25, 2016
- Altera Corporation
- Yanzhong Xu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Routing and programming for resistive switch arrays
- Patent number 9,432,023
- Issue date Aug 30, 2016
- Altera Corporation
- David Lewis
- G11 - INFORMATION STORAGE
Information Patent Grant
Heterogeneous programmable device and configuration software adapte...
- Patent number 9,401,718
- Issue date Jul 26, 2016
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multichip module with reroutable inter-die communication
- Patent number 9,368,451
- Issue date Jun 14, 2016
- Altera Corporation
- David Lewis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Clocking for pipelined routing
- Patent number 9,360,884
- Issue date Jun 7, 2016
- Altera Corporation
- David Galloway
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry for implementing multi-mode redundancy and arithmetic fun...
- Patent number 9,362,913
- Issue date Jun 7, 2016
- Altera Corporation
- Herman Henry Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory error detection circuitry
- Patent number 9,336,078
- Issue date May 10, 2016
- Altera Corporation
- Kostas Pagiamtzis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Metastability prediction and avoidance in memory arbitration circuitry
- Patent number 9,323,285
- Issue date Apr 26, 2016
- Altera Corporation
- David Lewis
- G11 - INFORMATION STORAGE
Information Patent Grant
Time division multiplexed multiport memory implemented using single...
- Patent number 9,298,211
- Issue date Mar 29, 2016
- Altera Corporation
- David Lewis
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit device configuration methods adapted to account...
- Patent number 9,245,085
- Issue date Jan 26, 2016
- Altera Corporation
- Ryan Fung
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
REGIONAL DESIGN-DEPENDENT VOLTAGE CONTROL AND CLOCKING
- Publication number 20180373831
- Publication date Dec 27, 2018
- Intel Corporation
- David Michael Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURES FOR LUT-BASED ARITHMETIC IN PLDS
- Publication number 20170322775
- Publication date Nov 9, 2017
- Altera Corporation
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINED INTERCONNECT CIRCUITRY WITH DOUBLE DATA RATE INTERCONNECT...
- Publication number 20170288671
- Publication date Oct 5, 2017
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Routing and Programming for Resistive Switch Arrays
- Publication number 20160344390
- Publication date Nov 24, 2016
- Altera Corporation
- David Lewis
- G11 - INFORMATION STORAGE
Information Patent Application
CLOCKING FOR PIPELINED ROUTING
- Publication number 20160239043
- Publication date Aug 18, 2016
- Altera Corporation
- David Galloway
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEVICE CONFIGURATION METHODS ADAPTED TO ACCOUNT...
- Publication number 20160098507
- Publication date Apr 7, 2016
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROUTING AND PROGRAMMING FOR RESISTIVE SWITCH ARRAYS
- Publication number 20160043724
- Publication date Feb 11, 2016
- Altera Corporation
- David Lewis
- G01 - MEASURING TESTING
Information Patent Application
CLOCKING FOR PIPELINED ROUTING
- Publication number 20150134870
- Publication date May 14, 2015
- Altera Corporation
- David Galloway
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METASTABILITY PREDICTION AND AVOIDANCE IN MEMORY ARBITRATION CIRCUITRY
- Publication number 20150052380
- Publication date Feb 19, 2015
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEVICE CONFIGURATION METHODS ADAPTED TO ACCOUNT...
- Publication number 20150033198
- Publication date Jan 29, 2015
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIME DIVISION MULTIPLEXED MULTIPORT MEMORY IMPLEMENTED USING SINGLE...
- Publication number 20140331074
- Publication date Nov 6, 2014
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE MULTI-GATE SWITCH CIRCUITRY
- Publication number 20140318937
- Publication date Oct 30, 2014
- David Lewis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS
- Publication number 20140258956
- Publication date Sep 11, 2014
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20140210515
- Publication date Jul 31, 2014
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE,...
- Publication number 20140082035
- Publication date Mar 20, 2014
- Altera Corporation
- Keone Streicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE,...
- Publication number 20130332497
- Publication date Dec 12, 2013
- Altera Corporation
- Keone Streicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus for Using Metastability-Hardened Storage Circuits in Logi...
- Publication number 20130328607
- Publication date Dec 12, 2013
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUITS WITH DUAL-EDGE CLOCKING
- Publication number 20130328606
- Publication date Dec 12, 2013
- Altera Corporation
- Ajay K. Ravi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUITS WITH MULTI-STAGE LOGIC REGIONS
- Publication number 20130257476
- Publication date Oct 3, 2013
- David Cashman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20130214815
- Publication date Aug 22, 2013
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUITS WITH SHARED INTERCONNECT BUSES
- Publication number 20130176052
- Publication date Jul 11, 2013
- Michael D. Hutton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Multichip Module with Reroutable Inter-Die Communication
- Publication number 20130168672
- Publication date Jul 4, 2013
- David Lewis
- G01 - MEASURING TESTING
Information Patent Application
TIME DIVISION MULTIPLEXED MULTIPORT MEMORY
- Publication number 20130111253
- Publication date May 2, 2013
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELAY CIRCUITRY
- Publication number 20120223754
- Publication date Sep 6, 2012
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20120217998
- Publication date Aug 30, 2012
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ERROR DETECTION AND CORRECTION CIRCUITRY
- Publication number 20120221919
- Publication date Aug 30, 2012
- Paul B. Ekas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROBUST TIME BORROWING PULSE LATCHES
- Publication number 20120112791
- Publication date May 10, 2012
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and Methods for Optimizing the Performance of Programmabl...
- Publication number 20120089958
- Publication date Apr 12, 2012
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUITS WITH DUAL-EDGE CLOCKING
- Publication number 20110304371
- Publication date Dec 15, 2011
- Ajay K. Ravi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-POWER ROUTING MULTIPLEXERS
- Publication number 20110267106
- Publication date Nov 3, 2011
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY

David Lewis

Person

Patents Grantslast 30 patents

Method and apparatus for performing symbolic timing analysis with s...

Regional design-dependent voltage control and clocking

Omnibus logic element

Pipelined interconnect circuitry with double data rate interconnect...

Regional design-dependent voltage control and clocking

Integrated circuit device configuration methods adapted to account...

Routing and programming for resistive switch arrays

Tristate multiplexers with immunity to aging effects

Techniques for bypassing defects in rows of circuits

Configurable storage blocks with embedded first-in first-out and de...

Circuitry for implementing multi-mode redundancy and arithmetic fun...

Metastability-hardened synchronization circuit

Pipelined interconnect circuitry with double data rate interconnect...

Integrated circuits with improved register circuitry

Structures for LUT-based arithmetic in PLDs

Error detection and correction circuitry

Methods and apparatus for detecting memory bit corruption on an int...

Configuring programmable integrated circuit device resources as pro...

First-in-first-out memory with dual memory banks

Omnibus logic element

Transition accelerator circuitry

Routing and programming for resistive switch arrays

Heterogeneous programmable device and configuration software adapte...

Multichip module with reroutable inter-die communication

Clocking for pipelined routing

Circuitry for implementing multi-mode redundancy and arithmetic fun...

Memory error detection circuitry

Metastability prediction and avoidance in memory arbitration circuitry

Time division multiplexed multiport memory implemented using single...

Integrated circuit device configuration methods adapted to account...

Patents Applicationslast 30 patents

REGIONAL DESIGN-DEPENDENT VOLTAGE CONTROL AND CLOCKING

STRUCTURES FOR LUT-BASED ARITHMETIC IN PLDS

PIPELINED INTERCONNECT CIRCUITRY WITH DOUBLE DATA RATE INTERCONNECT...

Routing and Programming for Resistive Switch Arrays

CLOCKING FOR PIPELINED ROUTING

INTEGRATED CIRCUIT DEVICE CONFIGURATION METHODS ADAPTED TO ACCOUNT...

ROUTING AND PROGRAMMING FOR RESISTIVE SWITCH ARRAYS

CLOCKING FOR PIPELINED ROUTING

METASTABILITY PREDICTION AND AVOIDANCE IN MEMORY ARBITRATION CIRCUITRY

INTEGRATED CIRCUIT DEVICE CONFIGURATION METHODS ADAPTED TO ACCOUNT...

TIME DIVISION MULTIPLEXED MULTIPORT MEMORY IMPLEMENTED USING SINGLE...

CONFIGURABLE MULTI-GATE SWITCH CIRCUITRY

APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE,...

MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE,...

Apparatus for Using Metastability-Hardened Storage Circuits in Logi...

INTEGRATED CIRCUITS WITH DUAL-EDGE CLOCKING

INTEGRATED CIRCUITS WITH MULTI-STAGE LOGIC REGIONS

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

INTEGRATED CIRCUITS WITH SHARED INTERCONNECT BUSES

Multichip Module with Reroutable Inter-Die Communication

TIME DIVISION MULTIPLEXED MULTIPORT MEMORY

DELAY CIRCUITRY

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

ERROR DETECTION AND CORRECTION CIRCUITRY

ROBUST TIME BORROWING PULSE LATCHES

Apparatus and Methods for Optimizing the Performance of Programmabl...

INTEGRATED CIRCUITS WITH DUAL-EDGE CLOCKING

LOW-POWER ROUTING MULTIPLEXERS