David LIN

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Palo Alto, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
System-level validation of systems-on-a-chip (SoC)
- Patent number 10,546,079
- Issue date Jan 28, 2020
- The Board of Trustees of the Leland Stanford Junior University
- Subhasish Mitra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-silicon validation and debug using symbolic quick error detection
- Patent number 10,528,448
- Issue date Jan 7, 2020
- The Board of Trustees of the Leland Stanford Junior University
- Subhasish Mitra
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM-LEVEL VALIDATION OF SYSTEMS-ON-A-CHIP (SoC)
- Publication number 20180165393
- Publication date Jun 14, 2018
- The Board of Trustees of the Leland Stanford Junior University
- Subhasish MITRA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POST-SILICON VALIDATION AND DEBUG USING SYMBOLIC QUICK ERROR DETECTION
- Publication number 20180157574
- Publication date Jun 7, 2018
- The Board of Trustees of the Leland Stanford Junior University
- Subhasish MITRA
- G06 - COMPUTING CALCULATING COUNTING