David Michael Moore

Person

Ann Arbor, MI, US

People

Patents Grantslast 30 patents

Information Patent Grant
Digital system synchronization
- Patent number 12,019,464
- Issue date Jun 25, 2024
- Movellus Circuits Inc.
- Jeffrey Alan Fredenburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing analysis for parallel multi-state driver circuits
- Patent number 11,017,138
- Issue date May 25, 2021
- Movellus Circuits, Inc.
- Jeffrey Fredenburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design system with automatic timing margin reduc...
- Patent number 10,740,526
- Issue date Aug 11, 2020
- Movellus Circuits, Inc.
- Jeffrey Fredenburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design system with automatic timing margin reduc...
- Patent number 10,713,409
- Issue date Jul 14, 2020
- Movellus Circuits, Inc.
- Jeffrey Fredenburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing analysis for electronic design automation of parallel multi-...
- Patent number 10,614,182
- Issue date Apr 7, 2020
- Movellus Circuits, Inc.
- Jeffrey Fredenburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrently optimized system-on-chip implementation with automatic...
- Patent number 10,031,992
- Issue date Jul 24, 2018
- Movellus Circuits, Inc.
- Jeffrey Fredenburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable phase-locked loop
- Patent number 9,762,249
- Issue date Sep 12, 2017
- Movellus Circuits, Inc.
- Muhammad Faisal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reconfigurable phase-locked loop with optional LC oscillator capabi...
- Patent number 9,705,516
- Issue date Jul 11, 2017
- Movellus Circuits, Inc.
- Jeffrey Alan Fredenburg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital controller for a phase-locked loop
- Patent number 9,698,798
- Issue date Jul 4, 2017
- Movellus Circuits, Inc.
- Jeffrey Alan Fredenburg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fractional and reconfigurable digital phase-locked loop
- Patent number 9,680,480
- Issue date Jun 13, 2017
- Movellus Circuits, Inc.
- Jeffrey Alan Fredenburg
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
DIGITAL SYSTEM SYNCHRONIZATION
- Publication number 20220200604
- Publication date Jun 23, 2022
- Movellus Circuits Incorporated
- Jeffrey Alan Fredenburg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TIMING ANALYSIS FOR PARALLEL MULTI-STATE DRIVER CIRCUITS
- Publication number 20200285794
- Publication date Sep 10, 2020
- Movellus Circuits Incorporated
- Jeffrey Fredenburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN SYSTEM WITH AUTOMATIC TIMING MARGIN REDUC...
- Publication number 20190213297
- Publication date Jul 11, 2019
- Movellus Circuits Incorporated
- Jeffrey Fredenburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONCURRENTLY OPTIMIZED SYSTEM-ON-CHIP IMPLEMENTATION WITH AUTOMATIC...
- Publication number 20190087516
- Publication date Mar 21, 2019
- Movellus Circuits Incorporated
- Jeffrey Fredenburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN SYSTEM WITH AUTOMATIC TIMING MARGIN REDUC...
- Publication number 20190050517
- Publication date Feb 14, 2019
- Movellus Circuits Incorporated
- Jeffrey Fredenburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONCURRENTLY OPTIMIZED SYSTEM-ON-CHIP IMPLEMENTATION WITH AUTOMATIC...
- Publication number 20180181684
- Publication date Jun 28, 2018
- Movellus Circuits Incorporated
- Jeffrey Fredenburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING ANALYSIS FOR ELECTRONIC DESIGN AUTOMATION OF PARALLEL MULTI-...
- Publication number 20180107774
- Publication date Apr 19, 2018
- Movellus Circuits Incorporated
- Jeffrey Fredenburg
- G06 - COMPUTING CALCULATING COUNTING

David Michael Moore

Person

Patents Grantslast 30 patents

Digital system synchronization

Timing analysis for parallel multi-state driver circuits

Integrated circuit design system with automatic timing margin reduc...

Integrated circuit design system with automatic timing margin reduc...

Timing analysis for electronic design automation of parallel multi-...

Concurrently optimized system-on-chip implementation with automatic...

Reconfigurable phase-locked loop

Reconfigurable phase-locked loop with optional LC oscillator capabi...

Digital controller for a phase-locked loop

Fractional and reconfigurable digital phase-locked loop

Patents Applicationslast 30 patents

DIGITAL SYSTEM SYNCHRONIZATION

TIMING ANALYSIS FOR PARALLEL MULTI-STATE DRIVER CIRCUITS

INTEGRATED CIRCUIT DESIGN SYSTEM WITH AUTOMATIC TIMING MARGIN REDUC...

CONCURRENTLY OPTIMIZED SYSTEM-ON-CHIP IMPLEMENTATION WITH AUTOMATIC...

INTEGRATED CIRCUIT DESIGN SYSTEM WITH AUTOMATIC TIMING MARGIN REDUC...

CONCURRENTLY OPTIMIZED SYSTEM-ON-CHIP IMPLEMENTATION WITH AUTOMATIC...

TIMING ANALYSIS FOR ELECTRONIC DESIGN AUTOMATION OF PARALLEL MULTI-...