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David N. Dixon
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Allison Park, PA, US
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last 30 patents
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Patent Grant
Technique for modeling parasitics from layout during circuit design...
Patent number
8,612,921
Issue date
Dec 17, 2013
Cadence Design Systems, Inc.
Prakash Gopalakrishnan
G06 - COMPUTING CALCULATING COUNTING
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Patent Grant
Technique for modeling parasitics from layout during circuit design...
Patent number
8,584,072
Issue date
Nov 12, 2013
Cadence Design Systems, Inc.
Prakash Gopalakrishnan
G06 - COMPUTING CALCULATING COUNTING
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Patent Grant
Technique for modeling parasitics from layout during circuit design...
Patent number
8,261,228
Issue date
Sep 4, 2012
Cadence Design Systems, Inc.
Prakash Gopalakrishnan
G06 - COMPUTING CALCULATING COUNTING