David Neto

Person

Toronto, CA

People

Patents Grantslast 30 patents

Information Patent Grant
M/A for compiling parallel program having barrier synchronization f...
- Patent number 10,599,404
- Issue date Mar 24, 2020
- Altera Corporation
- David Neto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for deriving signal activities for power analy...
- Patent number 10,417,362
- Issue date Sep 17, 2019
- Altera Corporation
- David Neto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Metastability-hardened synchronization circuit
- Patent number 9,697,309
- Issue date Jul 4, 2017
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for protecting, optimizing, and reporting sync...
- Patent number 9,342,640
- Issue date May 17, 2016
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-aware RAM processing
- Patent number 9,330,733
- Issue date May 3, 2016
- Altera Corporation
- Russell George Tessier
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for deriving signal activities for power analy...
- Patent number 8,898,603
- Issue date Nov 25, 2014
- Altera Corporation
- David Neto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for protecting, optimizing, and reporting sync...
- Patent number 8,732,639
- Issue date May 20, 2014
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for optimizing placement and routing
- Patent number 8,499,273
- Issue date Jul 30, 2013
- Altera Corporation
- Kimberley Anne Bozman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for deriving signal activities for power analy...
- Patent number 8,250,500
- Issue date Aug 21, 2012
- Altera Corporation
- David Neto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power reduction techniques for components in integrated circuits
- Patent number 8,015,425
- Issue date Sep 6, 2011
- Altera Corporation
- Aaron Charles Egier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for compiling programmable logic device config...
- Patent number 8,001,537
- Issue date Aug 16, 2011
- Altera Corporation
- Mihail Iotov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for deriving signal activities for power analy...
- Patent number 7,877,710
- Issue date Jan 25, 2011
- Altera Corporation
- David Neto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-aware RAM processing
- Patent number 7,877,555
- Issue date Jan 25, 2011
- Altera Corporation
- Russell George Tessier
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing dynamic power in a system
- Patent number 7,774,729
- Issue date Aug 10, 2010
- Altera Corporation
- David Neto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power reduction techniques for components in integrated circuits by...
- Patent number 7,587,620
- Issue date Sep 8, 2009
- Altera Corporation
- Aaron Charles Egier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer-aided-design tools for reducing power consumption in progr...
- Patent number 7,555,741
- Issue date Jun 30, 2009
- Altera Corporation
- David Ian M. Milton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock distribution for specialized processing block in programmable...
- Patent number 7,545,196
- Issue date Jun 9, 2009
- Altera Corporation
- Michael D. Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for identifying functional blocks in a design that match...
- Patent number 6,957,412
- Issue date Oct 18, 2005
- Altera Corporation
- Vaughn Betz
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

M/A for compiling parallel program having barrier synchronization f...

Method and apparatus for deriving signal activities for power analy...

Metastability-hardened synchronization circuit

Method and apparatus for protecting, optimizing, and reporting sync...

Power-aware RAM processing

Method and apparatus for deriving signal activities for power analy...

Method and apparatus for protecting, optimizing, and reporting sync...

Systems and methods for optimizing placement and routing

Method and apparatus for deriving signal activities for power analy...

Power reduction techniques for components in integrated circuits

Method and apparatus for compiling programmable logic device config...

Method and apparatus for deriving signal activities for power analy...

Power-aware RAM processing

Method and apparatus for reducing dynamic power in a system

Power reduction techniques for components in integrated circuits by...

Computer-aided-design tools for reducing power consumption in progr...

Clock distribution for specialized processing block in programmable...

Techniques for identifying functional blocks in a design that match...