David Patten

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Symmetric layout for high-voltage amplifier
- Patent number 11,942,468
- Issue date Mar 26, 2024
- Cirrus Logic, Inc.
- Aleksey Khenkin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered process-constructed double-winding embedded solenoid inductor
- Patent number 11,881,343
- Issue date Jan 23, 2024
- Cirrus Logic, Inc.
- Aleksey S. Khenkin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaging for MEMS transducers
- Patent number 11,299,392
- Issue date Apr 12, 2022
- Cirrus Logic, Inc.
- Rkia Achehboune
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Packaging for a MEMS transducer
- Patent number 11,252,513
- Issue date Feb 15, 2022
- Cirrus Logic, Inc.
- Roberto Brioschi
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
MEMS packaging
- Patent number 10,735,868
- Issue date Aug 4, 2020
- Cirrus Logic, Inc.
- Rkia Achehboune
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Transducer packaging
- Patent number 10,696,545
- Issue date Jun 30, 2020
- Cirrus Logic, Inc.
- Aleksey Sergeyevich Khenkin
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
MEMS transducer package
- Patent number 10,469,956
- Issue date Nov 5, 2019
- Cirrus Logic, Inc.
- Aleksey Sergeyevich Khenkin
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
MEMS transducer package
- Patent number 10,455,309
- Issue date Oct 22, 2019
- Cirrus Logic, Inc.
- Tsjerk Hoekstra
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
MEMS transducer package
- Patent number 10,334,339
- Issue date Jun 25, 2019
- Cirrus Logic, Inc.
- John Laurence Pennock
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Package for MEMS device and process
- Patent number 10,252,906
- Issue date Apr 9, 2019
- Cirrus Logic, Inc.
- Roberto Brioschi
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Stress decoupling in MEMS transducers
- Patent number 10,117,028
- Issue date Oct 30, 2018
- Cirrus Logic, Inc.
- David Talmage Patten
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Stackable molded packages and methods of making the same
- Patent number 8,044,494
- Issue date Oct 25, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Addi B. Mistry
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test interposer having active circuit component and method therefor
- Patent number 7,808,258
- Issue date Oct 5, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Marc A Mangrum
- G01 - MEASURING TESTING
Information Patent Grant
Digital and RF system and method therefor
- Patent number 7,479,407
- Issue date Jan 20, 2009
- FREESCALE SEMICONDUCTOR, INC.
- John Gehman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for testing a semiconductor structure having t...
- Patent number 7,262,615
- Issue date Aug 28, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Edmond Cheng
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
LAYERED PROCESS-CONSTRUCTED DOUBLE-WINDING EMBEDDED SOLENOID INDUCTOR
- Publication number 20240136105
- Publication date Apr 25, 2024
- Cirrus Logic International Semiconductor Ltd.
- Aleksey Khenkin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC CIRCUIT FABRICATION
- Publication number 20240128235
- Publication date Apr 18, 2024
- Cirrus Logic International Semiconductor Ltd.
- David PATTEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYMMETRIC LAYOUT FOR HIGH-VOLTAGE AMPLIFIER
- Publication number 20220384413
- Publication date Dec 1, 2022
- Cirrus Logic International Semiconductor Ltd.
- Aleksey Khenkin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUITS WITH EMBEDDED LAYERS
- Publication number 20220376035
- Publication date Nov 24, 2022
- Cirrus Logic International Semiconductor Ltd.
- David PATTEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYERED PROCESS-CONSTRUCTED DOUBLE-WINDING EMBEDDED SOLENOID INDUCTOR
- Publication number 20210287841
- Publication date Sep 16, 2021
- Aleksey S. Khenkin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONFORMAL SHIELD FOR BLOCKING LIGHT IN AN INTEGRATED CIRCUIT PACKAGE
- Publication number 20210111131
- Publication date Apr 15, 2021
- Cirrus Logic International Semiconductor Ltd.
- John PAVELKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGING FOR MEMS TRANSDUCERS
- Publication number 20200377363
- Publication date Dec 3, 2020
- Cirrus Logic International Semiconductor Ltd.
- Rkia ACHEHBOUNE
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
PACKAGING FOR A MEMS TRANSDUCER
- Publication number 20200369514
- Publication date Nov 26, 2020
- Cirrus Logic International Semiconductor Ltd.
- Roberto BRIOSCHI
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
PACKAGING FOR A MEMS TRANSDUCER
- Publication number 20200304921
- Publication date Sep 24, 2020
- Cirrus Logic International Semiconductor Ltd.
- Roberto BRIOSCHI
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
MEMS PACKAGING
- Publication number 20190158962
- Publication date May 23, 2019
- Cirrus Logic International Semiconductor Ltd.
- Rkia ACHEHBOUNE
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
TRANSDUCER PACKAGING
- Publication number 20180362332
- Publication date Dec 20, 2018
- Cirrus Logic International Semiconductor Ltd.
- Aleksey Sergeyevich KHENKIN
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
MEMS Transducer Package
- Publication number 20180279057
- Publication date Sep 27, 2018
- Cirrus Logic International Semiconductor Ltd.
- Aleksey Sergeyevich KHENKIN
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
PACKAGE FOR MEMS DEVICE AND PROCESS
- Publication number 20180127265
- Publication date May 10, 2018
- Cirrus Logic International Semiconductor Ltd.
- Roberto BRIOSCHI
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
MEMS TRANSDUCER PACKAGE
- Publication number 20170374441
- Publication date Dec 28, 2017
- Cirrus Logic International Semiconductor Ltd.
- Tsjerk HOEKSTRA
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
MEMS TRANSDUCER PACKAGE
- Publication number 20170374473
- Publication date Dec 28, 2017
- Cirrus Logic International Semiconductor Ltd.
- Tsjerk HOEKSTRA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MEMS TRANSDUCER PACKAGE
- Publication number 20170374442
- Publication date Dec 28, 2017
- Cirrus Logic International Semiconductor Ltd.
- John Laurence PENNOCK
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
STRESS DECOUPLING IN MEMS TRANSDUCERS
- Publication number 20170223466
- Publication date Aug 3, 2017
- Cirrus Logic International Semiconductor Ltd.
- David Talmage PATTEN
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
SYSTEMS AND METHODS FOR CARRYING SINGULATED DEVICE PACKAGES
- Publication number 20150303171
- Publication date Oct 22, 2015
- Cirrus Logic, Inc.
- David T. Patten
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKABLE MOLDED PACKAGES AND METHODS OF MAKING THE SAME
- Publication number 20100013065
- Publication date Jan 21, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Addi B. Mistry
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TEST INTERPOSER HAVING ACTIVE CIRCUIT COMPONENT AND METHOD THEREFOR
- Publication number 20090322364
- Publication date Dec 31, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Marc A. Mangrum
- G01 - MEASURING TESTING
Information Patent Application
STACKABLE MOLDED PACKAGES AND METHODS OF MAKING THE SAME
- Publication number 20080108179
- Publication date May 8, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Addi B. Mistry
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stackable molded packages and methods of making the same
- Publication number 20070141751
- Publication date Jun 21, 2007
- Addi B. Mistry
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for testing a semiconductor structure having t...
- Publication number 20070096760
- Publication date May 3, 2007
- Edmond Cheng
- G01 - MEASURING TESTING
Information Patent Application
Digital and RF system and method therefor
- Publication number 20040195591
- Publication date Oct 7, 2004
- John Gehman
- H01 - BASIC ELECTRIC ELEMENTS

David Patten

Person

Patents Grantslast 30 patents

Symmetric layout for high-voltage amplifier

Layered process-constructed double-winding embedded solenoid inductor

Packaging for MEMS transducers

Packaging for a MEMS transducer

MEMS packaging

Transducer packaging

MEMS transducer package

MEMS transducer package

MEMS transducer package

Package for MEMS device and process

Stress decoupling in MEMS transducers

Stackable molded packages and methods of making the same

Test interposer having active circuit component and method therefor

Digital and RF system and method therefor

Method and apparatus for testing a semiconductor structure having t...

Patents Applicationslast 30 patents

LAYERED PROCESS-CONSTRUCTED DOUBLE-WINDING EMBEDDED SOLENOID INDUCTOR

ELECTRONIC CIRCUIT FABRICATION

SYMMETRIC LAYOUT FOR HIGH-VOLTAGE AMPLIFIER

INTEGRATED CIRCUITS WITH EMBEDDED LAYERS

LAYERED PROCESS-CONSTRUCTED DOUBLE-WINDING EMBEDDED SOLENOID INDUCTOR

CONFORMAL SHIELD FOR BLOCKING LIGHT IN AN INTEGRATED CIRCUIT PACKAGE

PACKAGING FOR MEMS TRANSDUCERS

PACKAGING FOR A MEMS TRANSDUCER

PACKAGING FOR A MEMS TRANSDUCER

MEMS PACKAGING

TRANSDUCER PACKAGING

MEMS Transducer Package

PACKAGE FOR MEMS DEVICE AND PROCESS

MEMS TRANSDUCER PACKAGE

MEMS TRANSDUCER PACKAGE

MEMS TRANSDUCER PACKAGE

STRESS DECOUPLING IN MEMS TRANSDUCERS

SYSTEMS AND METHODS FOR CARRYING SINGULATED DEVICE PACKAGES

STACKABLE MOLDED PACKAGES AND METHODS OF MAKING THE SAME

TEST INTERPOSER HAVING ACTIVE CIRCUIT COMPONENT AND METHOD THEREFOR

STACKABLE MOLDED PACKAGES AND METHODS OF MAKING THE SAME

Stackable molded packages and methods of making the same

Method and apparatus for testing a semiconductor structure having t...

Digital and RF system and method therefor